Re: [Qemu-devel] e1000 autoneg timing, piix/osx

[Gabriel L. Somlo]

On Thu, Jul 03, 2014 at 05:25:04PM +0200, Alexander Graf wrote:
> Maybe the IRQ line is simply never shared on real Macs :). Who knows.
> 
> Does this (untested!) patch make it work for you?

Yep, it works. Doesn't break OSX on q35, Linux (F20) or windows (7)
either :)

Thanks,
--Gabriel

> diff --git a/hw/net/e1000.c b/hw/net/e1000.c
> index 0fc29a0..7db0538 100644
> --- a/hw/net/e1000.c
> +++ b/hw/net/e1000.c
> @@ -1090,9 +1090,24 @@ static uint32_t
>  mac_icr_read(E1000State *s, int index)
>  {
>      uint32_t ret = s->mac_reg[ICR];
> +    uint32_t new_icr = 0;
> 
>      DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
> -    set_interrupt_cause(s, 0, 0);
> +
> +    /*
> +     * Mac OS X reads ICR on every interrupt. When the IRQ line is shared,
> +     * this may result in a race where LSC is not interpreted yet, but
> +     * already gets cleared.
> +     *
> +     * The easiest fix is to delay LSC events until after they have been
> +     * property unmasked, so let's just claim we never saw any here.
> +     */
> +    if ((ret & E1000_ICS_LSC) && !(s->mac_reg[IMS] & E1000_ICS_LSC)) {
> +        ret &= ~E1000_ICS_LSC;
> +        new_icr |= E1000_ICS_LSC;
> +    }
> +
> +    set_interrupt_cause(s, 0, new_icr);
>      return ret;
>  }
>