[Qemu-devel] [PATCH 13/15] target-tricore: Add instructions of SC opcode format

[Bastian Koppelmann]

Add instructions of SC opcode format.
Add makro to generate helper with 1 arg.
Add micro-op generator functions for indirect loads.

Signed-off-by: Bastian Koppelmann <address@hidden>
---
 target-tricore/helper.h    |  2 +-
 target-tricore/op_helper.c | 40 +++++++++++++++++++++++++++++++++++++
 target-tricore/translate.c | 49 ++++++++++++++++++++++++++++++++++++++++++++--
 3 files changed, 88 insertions(+), 3 deletions(-)

diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index 0d79d1d..8d70784 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -21,4 +21,4 @@ DEF_HELPER_3(shac, i32, env, i32, i32)
 /* CSA */
 DEF_HELPER_3(call, void, env, i32, i32)
 DEF_HELPER_1(ret, void, env)
-
+DEF_HELPER_2(bisr, void, env, i32)
diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index 5267fd0..499697b 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -248,6 +248,46 @@ void helper_ret(CPUTRICOREState *env)
     env->active_tc.PCXI = new_PCXI;
 }
 
+void helper_bisr(CPUTRICOREState *env, uint32_t const9)
+{
+    target_ulong tmp_FCX;
+    target_ulong ea;
+    target_ulong new_FCX;
+
+    if (env->active_tc.FCX == 0) {
+        printf("FCU trap\n");
+    }
+
+    tmp_FCX = env->active_tc.FCX;
+    ea = ((env->active_tc.FCX & 0xf0000) << 12) +
+         ((env->active_tc.FCX & 0xffff) << 6);
+
+    save_context(env, ea, 0, &new_FCX);
+
+    /* PCXI.PCPN = ICR.CCPN */
+    env->active_tc.PCXI = (env->active_tc.PCXI & 0xffffff) +
+                          ((env->active_tc.ICR & MASK_ICR_CCPN) << 24);
+    /* PCXI.PIE  = ICR.IE */
+    env->active_tc.PCXI = ((env->active_tc.PCXI & ~MASK_PCXI_PIE) +
+                           ((env->active_tc.ICR & MASK_ICR_IE) << 15));
+    /* PCXI.UL = 0 */
+    env->active_tc.PCXI &= ~(MASK_PCXI_UL);
+    /* PCXI[19: 0] = FCX[19: 0] */
+    env->active_tc.PCXI = (env->active_tc.PCXI & 0xfff00000) +
+                          (env->active_tc.FCX & 0xfffff);
+    /* FXC[19: 0] = new_FCX[19: 0] */
+    env->active_tc.FCX = (env->active_tc.FCX & 0xfff00000) +
+                         (new_FCX & 0xfffff);
+    /* ICR.IE = 1 */
+    env->active_tc.ICR |= MASK_ICR_IE;
+
+    env->active_tc.ICR |= (const9 & 0xff); /* ICR.CCPN = const9[7: 0];*/
+
+    if (tmp_FCX == env->active_tc.LCX) {
+        printf("FCD trap\n");
+    }
+}
+
 static inline void QEMU_NORETURN do_raise_exception_err(CPUTRICOREState *env,
                                                         uint32_t exception,
                                                         int error_code,
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 5b11396..e98af65 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -118,6 +118,11 @@ static int sign_extend(uint32_t val, uint32_t width)
  */
 
 /* Makros for generating helpers */
+#define gen_helper_1arg(name, arg) do {                           \
+    TCGv_i32 helper_tmp = tcg_const_i32(arg);                     \
+    gen_helper_##name(cpu_env, helper_tmp);                       \
+    tcg_temp_free_i32(helper_tmp);                                \
+    } while (0)
 #define gen_helper_2arg(name, arg0, arg1) do {                    \
     TCGv_i32 helper_tmp0 = tcg_const_i32(arg0);                   \
     TCGv_i32 helper_tmp1 = tcg_const_i32(arg1);                   \
@@ -145,6 +150,10 @@ OP_MEM_INDIRECT(ld16u)
 OP_MEM_INDIRECT(ld32s)
 OP_MEM_INDIRECT(ld32u)
 
+OP_MEM_INDIRECT(st8)
+OP_MEM_INDIRECT(st16)
+OP_MEM_INDIRECT(st32)
+
 /* Functions for arithmetic instructions  */
 
 #define OP_COND(insn)\
@@ -737,8 +746,44 @@ static void decode_16Bit_opc(CPUTRICOREState *env, 
DisasContext *ctx)
         address = MASK_OP_SBR_DISP4(ctx->opcode);
         gen_compute_branch(ctx, op1, r1, 0, 0, address);
         break;
-
-   }
+/* SC-format */
+    case OPC1_16_SC_AND:
+        const16 = MASK_OP_SC_CONST8(ctx->opcode);
+        tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
+        break;
+    case OPC1_16_SC_BISR:
+        const16 = MASK_OP_SC_CONST8(ctx->opcode);
+        gen_helper_1arg(bisr, const16);
+        break;
+    case OPC1_16_SC_LD_A:
+        const16 = MASK_OP_SC_CONST8(ctx->opcode);
+        gen_indirect_ld32s(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4);
+        break;
+    case OPC1_16_SC_LD_W:
+        const16 = MASK_OP_SC_CONST8(ctx->opcode);
+        gen_indirect_ld32s(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4);
+        break;
+    case OPC1_16_SC_MOV:
+        const16 = MASK_OP_SC_CONST8(ctx->opcode);
+        tcg_gen_movi_tl(cpu_gpr_d[15], const16);
+        break;
+    case OPC1_16_SC_OR:
+        const16 = MASK_OP_SC_CONST8(ctx->opcode);
+        tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
+        break;
+    case OPC1_16_SC_ST_A:
+        const16 = MASK_OP_SC_CONST8(ctx->opcode);
+        gen_indirect_st32(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4);
+        break;
+    case OPC1_16_SC_ST_W:
+        const16 = MASK_OP_SC_CONST8(ctx->opcode);
+        gen_indirect_st32(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4);
+        break;
+    case OPC1_16_SC_SUB_A:
+        const16 = MASK_OP_SC_CONST8(ctx->opcode);
+        tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
+        break;
+    }
 }
 
 static void decode_32Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
-- 
2.0.1