Re: [Qemu-devel] [PATCH 07/15] target-tricore: Add instructions of SRR opcode format

[Richard Henderson]

On 07/07/2014 11:13 AM, Bastian Koppelmann wrote:
> Add instructions of SRR opcode format.
> Add micro-op generator function for ssov.
> 
> Signed-off-by: Bastian Koppelmann <address@hidden>
> ---
>  target-tricore/translate.c | 140 
> ++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 139 insertions(+), 1 deletion(-)
> 
> diff --git a/target-tricore/translate.c b/target-tricore/translate.c
> index ad595b2..108619c 100644
> --- a/target-tricore/translate.c
> +++ b/target-tricore/translate.c
> @@ -203,14 +203,34 @@ static void gen_shaci(TCGv ret, TCGv r1, int32_t con)
>      tcg_temp_free(temp);
>  }
>  
> +static inline void gen_ssov(TCGv ret, TCGv arg, int32_t cons)
> +{
> +    int l1 = gen_new_label();
> +    TCGv temp = tcg_temp_local_new();
> +    int32_t max_pos = (0x1u << (cons - 1)) - 1;
> +    int32_t max_neg = -(0x1u << (cons - 1));
> +
> +    tcg_gen_movi_tl(temp, max_pos);
> +    tcg_gen_brcondi_tl(TCG_COND_GT, arg, max_pos, l1);
> +    tcg_gen_movi_tl(temp, max_neg);
> +    tcg_gen_brcondi_tl(TCG_COND_LT, arg, max_neg, l1);
> +    tcg_gen_mov_tl(temp, arg);
> +    gen_set_label(l1);
> +    tcg_gen_mov_tl(ret, temp);
> +
> +    tcg_temp_free(temp);
> +}

Movcond, but...

> +    case OPC1_16_SRR_ADDS:
> +        r2 = MASK_OP_SRR_S2(ctx->opcode);
> +        r1 = MASK_OP_SRR_S1D(ctx->opcode);
> +
> +        temp = tcg_temp_local_new();
> +        tcg_gen_add_tl(temp, cpu_gpr_d[r1], cpu_gpr_d[r2]);
> +        gen_ssov(cpu_gpr_d[r1], temp, 32);
> +        tcg_temp_free(temp);
> +        break;

... you can't detect 32-bit overflow this way.  One has to use 33-bit (or more)
arithmetic to perform the comparisons that you use here.

There are several ways this could be open-coded in TCG, but I'd be surprised if
this insn is used often enough to be worth it.  It'll be simpler and easier to
just use a helper function.

> +    case OPC1_16_SRR_SUBS:

Likewise.


r~