Re: [Qemu-devel] [PATCH 06/15] target-tricore: Add instructions of SRC opcode format

[Max Filippov]

Hi Bastian,

On Mon, Jul 7, 2014 at 10:13 PM, Bastian Koppelmann
<address@hidden> wrote:
> Add instructions of SRC opcode format.
> Add helper for sh arithmetic carry.
> Add micro-op generator functions for conditional add/sub/mov and sh.
>
> Signed-off-by: Bastian Koppelmann <address@hidden>
> ---
>  target-tricore/helper.h    |  19 +++++
>  target-tricore/op_helper.c |  36 +++++++++
>  target-tricore/translate.c | 197 
> ++++++++++++++++++++++++++++++++++++++++++++-
>  3 files changed, 251 insertions(+), 1 deletion(-)
>
> diff --git a/target-tricore/helper.h b/target-tricore/helper.h
> index e69de29..acea104 100644
> --- a/target-tricore/helper.h
> +++ b/target-tricore/helper.h

[...]

> +target_ulong helper_shac(CPUTRICOREState *env, target_ulong r1,
> +                target_ulong r2)
> +{
> +    target_ulong carry_out, msk, msk_start, msk_len, cond, shift_count, ret;
> +    int const6;
> +    const6 = r2 & 0x3f;
> +
> +    if (const6 >= 0) {

There's no way const6 may be negative here, if you meant 'negative 6-bit-wide
signed integer' then you need to change the way you calculate const6 to e.g.
const6 = sextract32(r2, 0, 6);

-- 
Thanks.
-- Max