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[Qemu-devel] [PATCH v2 0/9] target-mips: implement features required in
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PATCH v2 0/9] target-mips: implement features required in MIPS64 Release 6 |
Date: |
Tue, 8 Jul 2014 08:57:28 +0100 |
This patch series implement set of features whose presence became mandatory in
MIPS64R6:
- KScratch registers,
- Read-Inhibit and Execute-Inhibit page protection bits,
- TLB Invalidate (TLBINV and TLBINVF instructions),
- BadInstr and BadInstrP.
This series should be applied on the top of pending patches introducing
MIPS64R6 Instruction Set.
Commits briefly describe each feature. For more details please refer to the
Volume III (The MIPS64 and microMIPS64 Privileged Resource Architecture) and
Volume II (The MIPS64 Instruction Set) of MIPS documents available at:
http://www.imgtec.com/mips/architectures/mips64.asp
This patchset focuses on features which existed before Release 6. It does not
contain new MIPS64R6 features like forbidden slot, SBRI, reserved fields.
This will come as a separate patchset soon.
Any comments / suggestions are more than welcome!
Thanks,
Leon
v2:
* changed BadInstr implementation - fetching instruction word instead of
generating code to save the last instruction,
* dropped patch updating cpu configuration - this will be done later, when all
the required features are implemented,
* modified mtc0 and mfc0 to behave like on the real HW when referring to
an unimplemented cp0 register (new registers only)
* updated CPU_SAVE_VERSION,
* added a patch to the series providing mmu_access_type enum.
Leon Alrae (9):
target-mips: add KScratch registers
softmmu: provide softmmu access type enum
target-mips: distinguish between data load and instruction fetch
target-mips: add RI and XI fields to TLB entry
target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}
target-mips: add new Read-Inhibit and Execute-Inhibit exceptions
target-mips: add TLBINV support
target-mips: add BadInstr and BadInstrP support
target-mips: update cpu_save/cpu_load to support new registers
disas/mips.c | 2 +
include/exec/cpu-common.h | 6 ++
softmmu_template.h | 26 ++++---
target-mips/cpu.h | 38 +++++++++-
target-mips/helper.c | 103 +++++++++++++++++++++----
target-mips/helper.h | 7 ++
target-mips/machine.c | 14 ++++
target-mips/op_helper.c | 115 +++++++++++++++++++++++++---
target-mips/translate.c | 172 ++++++++++++++++++++++++++++++++++++++++--
target-mips/translate_init.c | 4 +
10 files changed, 438 insertions(+), 49 deletions(-)
--
1.7.5.4
- [Qemu-devel] [PATCH v2 0/9] target-mips: implement features required in MIPS64 Release 6,
Leon Alrae <=
- [Qemu-devel] [PATCH v2 6/9] target-mips: add new Read-Inhibit and Execute-Inhibit exceptions, Leon Alrae, 2014/07/08
- [Qemu-devel] [PATCH v2 5/9] target-mips: update PageGrain and m{t, f}c0 EntryLo{0, 1}, Leon Alrae, 2014/07/08
- [Qemu-devel] [PATCH v2 4/9] target-mips: add RI and XI fields to TLB entry, Leon Alrae, 2014/07/08
- [Qemu-devel] [PATCH v2 7/9] target-mips: add TLBINV support, Leon Alrae, 2014/07/08