Re: [Qemu-devel] [PATCH 08/12] target-mips: add BadInstr and BadInstrP support

[Leon Alrae]

On 19/06/2014 23:13, Aurelien Jarno wrote:
> I don't think this should implemented that way, as it would have a
> significant impact on the performances. Given we have the fault address
> (we fill EPC), we can fetch the corresponding opcode. There might be
> some code change to do for the branches, so that we can get the
> informations we need from re-translation (this might also simplify the
> current branches code).

I changed the BadInstr implementation in v2. Now the instruction word is
fetched when we have the exception (and the valid instruction word is
available), so we don't have to generate code to save the last
instruction. The same has been done for BadInstrP and the branch prior
to the delay slot.

Thanks,
Leon