Re: [Qemu-devel] [PATCH v2 8/9] target-mips: add BadInstr and BadInstrP support

[James Hogan]

Hi Leon,

On 08/07/14 08:57, Leon Alrae wrote:
> BadInstr Register (CP0 Register 8, Select 1)
> The BadInstr register is a read-only register that capture the most recent
> instruction which caused an exception.
> 
> BadInstrP Register (CP0 Register 8, Select 2)
> The BadInstrP register contains the prior branch instruction, when the
> faulting instruction is in a branch delay slot.
> 
> Using error_code to indicate whether AdEL or TLBL was triggered during
> instruction fetch, in this case BadInstr is not updated as valid instruction
> word is not available.
> 
> Signed-off-by: Leon Alrae <address@hidden>
> ---
>  target-mips/cpu.h       |    6 +++
>  target-mips/helper.c    |   44 ++++++++++++++++++++++++--
>  target-mips/op_helper.c |   17 +++++++++-
>  target-mips/translate.c |   80 +++++++++++++++++++++++++++++++++++++++++++---
>  4 files changed, 136 insertions(+), 11 deletions(-)
> 
> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> index bc52222..656f5ca 100644
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -177,6 +177,8 @@ struct TCState {
>      target_ulong CP0_TCScheFBack;
>      int32_t CP0_Debug_tcstatus;
>      target_ulong CP0_UserLocal;
> +    uint32_t CP0_BadInstr;
> +    uint32_t CP0_BadInstrP;

According to the PRA, BadInstr/BadInstrP are instantiated per VPE, so
shouldn't these be in struct CPUMIPSState?

Cheers
James