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[Qemu-devel] [PULL 06/18] target-alpha: Raise IOV from CVTTQ
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 06/18] target-alpha: Raise IOV from CVTTQ |
Date: |
Wed, 9 Jul 2014 09:20:22 -0700 |
Floating-point overflow is a different bit from integer overflow.
Reported-by: Al Viro <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-alpha/fpu_helper.c | 25 ++++++++++---------------
target-alpha/helper.h | 1 -
target-alpha/translate.c | 17 ++++-------------
3 files changed, 14 insertions(+), 29 deletions(-)
diff --git a/target-alpha/fpu_helper.c b/target-alpha/fpu_helper.c
index 8bd4c08..19f3ebc 100644
--- a/target-alpha/fpu_helper.c
+++ b/target-alpha/fpu_helper.c
@@ -693,12 +693,10 @@ uint64_t helper_cvtqs(CPUAlphaState *env, uint64_t a)
/* Implement float64 to uint64 conversion without saturation -- we must
supply the truncated result. This behaviour is used by the compiler
- to get unsigned conversion for free with the same instruction.
-
- The VI flag is set when overflow or inexact exceptions should be raised. */
+ to get unsigned conversion for free with the same instruction. */
static inline uint64_t inline_cvttq(CPUAlphaState *env, uint64_t a,
- int roundmode, int VI)
+ int roundmode)
{
uint64_t frac, ret = 0;
uint32_t exp, sign, exc = 0;
@@ -713,7 +711,8 @@ static inline uint64_t inline_cvttq(CPUAlphaState *env,
uint64_t a,
goto do_underflow;
}
} else if (exp == 0x7ff) {
- exc = (frac ? float_flag_invalid : VI ? float_flag_overflow : 0);
+ exc = (frac ? float_flag_invalid
+ : float_flag_int_overflow | float_flag_inexact);
} else {
/* Restore implicit bit. */
frac |= 0x10000000000000ull;
@@ -722,10 +721,11 @@ static inline uint64_t inline_cvttq(CPUAlphaState *env,
uint64_t a,
if (shift >= 0) {
/* In this case the number is so large that we must shift
the fraction left. There is no rounding to do. */
+ exc = float_flag_int_overflow | float_flag_inexact;
if (shift < 63) {
ret = frac << shift;
- if (VI && (ret >> shift) != frac) {
- exc = float_flag_overflow;
+ if ((ret >> shift) == frac) {
+ exc = 0;
}
}
} else {
@@ -748,7 +748,7 @@ static inline uint64_t inline_cvttq(CPUAlphaState *env,
uint64_t a,
}
if (round) {
- exc = (VI ? float_flag_inexact : 0);
+ exc = float_flag_inexact;
switch (roundmode) {
case float_round_nearest_even:
if (round == (1ull << 63)) {
@@ -782,17 +782,12 @@ static inline uint64_t inline_cvttq(CPUAlphaState *env,
uint64_t a,
uint64_t helper_cvttq(CPUAlphaState *env, uint64_t a)
{
- return inline_cvttq(env, a, FP_STATUS.float_rounding_mode, 1);
+ return inline_cvttq(env, a, FP_STATUS.float_rounding_mode);
}
uint64_t helper_cvttq_c(CPUAlphaState *env, uint64_t a)
{
- return inline_cvttq(env, a, float_round_to_zero, 0);
-}
-
-uint64_t helper_cvttq_svic(CPUAlphaState *env, uint64_t a)
-{
- return inline_cvttq(env, a, float_round_to_zero, 1);
+ return inline_cvttq(env, a, float_round_to_zero);
}
uint64_t helper_cvtqt(CPUAlphaState *env, uint64_t a)
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index a451cfe..173db01 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -83,7 +83,6 @@ DEF_HELPER_FLAGS_2(cvtqg, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_2(cvttq, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_2(cvttq_c, TCG_CALL_NO_RWG, i64, env, i64)
-DEF_HELPER_FLAGS_2(cvttq_svic, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_2(setroundmode, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(setflushzero, TCG_CALL_NO_RWG, void, env, i32)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 1c2d72e..183573d 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -771,23 +771,14 @@ static void gen_fcvttq(DisasContext *ctx, int rb, int rc,
int fn11)
vb = gen_ieee_input(ctx, rb, fn11, 0);
vc = dest_fpr(ctx, rc);
- /* Almost all integer conversions use cropped rounding, and most
- also do not have integer overflow enabled. Special case that. */
- switch (fn11) {
- case QUAL_RM_C:
+ /* Almost all integer conversions use cropped rounding;
+ special case that. */
+ if ((fn11 & QUAL_RM_MASK) == QUAL_RM_C) {
gen_helper_cvttq_c(vc, cpu_env, vb);
- break;
- case QUAL_V | QUAL_RM_C:
- case QUAL_S | QUAL_V | QUAL_RM_C:
- case QUAL_S | QUAL_V | QUAL_I | QUAL_RM_C:
- gen_helper_cvttq_svic(vc, cpu_env, vb);
- break;
- default:
+ } else {
gen_qual_roundmode(ctx, fn11);
gen_helper_cvttq(vc, cpu_env, vb);
- break;
}
-
gen_fp_exc_raise(rc, fn11);
}
--
1.9.3
- [Qemu-devel] [PULL for-2.1 00/18] target-alpha patch queue, Richard Henderson, 2014/07/10
- [Qemu-devel] [PULL 07/18] target-alpha: Fix cvttq vs large integers, Richard Henderson, 2014/07/09
- [Qemu-devel] [PULL 06/18] target-alpha: Raise IOV from CVTTQ,
Richard Henderson <=
- [Qemu-devel] [PULL 08/18] target-alpha: Fix cvttq vs inf, Richard Henderson, 2014/07/09
- Message not available
- Re: [Qemu-devel] [PULL for-2.1 00/18] target-alpha patch queue, Peter Maydell, 2014/07/09
- [Qemu-devel] [PULL 10/18] target-alpha: Implement WH64EN, Richard Henderson, 2014/07/09
- [Qemu-devel] [PULL 04/18] target-alpha: Set fpcr_exc_status even for disabled exceptions, Richard Henderson, 2014/07/09
- [Qemu-devel] [PULL 02/18] target-alpha: Set PC correctly for floating-point exceptions, Richard Henderson, 2014/07/09
- [Qemu-devel] [PULL 16/18] target-alpha: Rename fcvtql, Richard Henderson, 2014/07/09
- [Qemu-devel] [PULL 15/18] target-alpha: Raise IOV from CVTQL, Richard Henderson, 2014/07/09