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[Qemu-devel] [PULL 15/18] target-alpha: Raise IOV from CVTQL
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 15/18] target-alpha: Raise IOV from CVTQL |
Date: |
Wed, 9 Jul 2014 09:20:31 -0700 |
Even if an exception isn't taken, the status flags need updating
and the result should be written to the destination. Move the body
of cvtql out of line, since we now always need a call.
Reported-by: Al Viro <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-alpha/fpu_helper.c | 8 ++++++--
target-alpha/helper.h | 3 ++-
target-alpha/translate.c | 34 +++++-----------------------------
3 files changed, 13 insertions(+), 32 deletions(-)
diff --git a/target-alpha/fpu_helper.c b/target-alpha/fpu_helper.c
index 796d907..67d9a5b 100644
--- a/target-alpha/fpu_helper.c
+++ b/target-alpha/fpu_helper.c
@@ -842,9 +842,13 @@ uint64_t helper_cvtqg(CPUAlphaState *env, uint64_t a)
return float64_to_g(fr);
}
-void helper_fcvtql_v_input(CPUAlphaState *env, uint64_t val)
+uint64_t helper_cvtql(CPUAlphaState *env, uint64_t val)
{
+ int exc = 0;
if (val != (int32_t)val) {
- arith_excp(env, GETPC(), EXC_M_IOV, 0);
+ exc = float_flag_int_overflow | float_flag_inexact;
}
+ set_float_exception_flags(exc, &FP_STATUS);
+
+ return ((val & 0xc0000000) << 32) | ((val & 0x3fffffff) << 29);
}
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index 596f24d..128f7a1 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -79,6 +79,8 @@ DEF_HELPER_FLAGS_2(cvtqg, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_2(cvttq, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_2(cvttq_c, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(cvtql, TCG_CALL_NO_RWG, i64, env, i64)
+
DEF_HELPER_FLAGS_2(setroundmode, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(setflushzero, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_1(fp_exc_clear, TCG_CALL_NO_RWG, void, env)
@@ -89,7 +91,6 @@ DEF_HELPER_FLAGS_3(fp_exc_raise_s, TCG_CALL_NO_WG, void, env,
i32, i32)
DEF_HELPER_FLAGS_2(ieee_input, TCG_CALL_NO_WG, void, env, i64)
DEF_HELPER_FLAGS_2(ieee_input_cmp, TCG_CALL_NO_WG, void, env, i64)
DEF_HELPER_FLAGS_2(ieee_input_s, TCG_CALL_NO_WG, void, env, i64)
-DEF_HELPER_FLAGS_2(fcvtql_v_input, TCG_CALL_NO_WG, void, env, i64)
#if !defined (CONFIG_USER_ONLY)
DEF_HELPER_2(hw_ret, void, env, i64)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 3a7c2ba..8ad098a 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -729,19 +729,6 @@ static void gen_fcvtlq(TCGv vc, TCGv vb)
tcg_temp_free(tmp);
}
-static void gen_fcvtql(TCGv vc, TCGv vb)
-{
- TCGv tmp = tcg_temp_new();
-
- tcg_gen_andi_i64(tmp, vb, (int32_t)0xc0000000);
- tcg_gen_andi_i64(vc, vb, 0x3FFFFFFF);
- tcg_gen_shli_i64(tmp, tmp, 32);
- tcg_gen_shli_i64(vc, vc, 29);
- tcg_gen_or_i64(vc, vc, tmp);
-
- tcg_temp_free(tmp);
-}
-
static void gen_ieee_arith2(DisasContext *ctx,
void (*helper)(TCGv, TCGv_ptr, TCGv),
int rb, int rc, int fn11)
@@ -2269,25 +2256,14 @@ static ExitStatus translate_one(DisasContext *ctx,
uint32_t insn)
/* FCMOVGT */
gen_fcmov(ctx, TCG_COND_GT, ra, rb, rc);
break;
- case 0x030:
- /* CVTQL */
- REQUIRE_REG_31(ra);
- vc = dest_fpr(ctx, rc);
- vb = load_fpr(ctx, rb);
- gen_fcvtql(vc, vb);
- break;
- case 0x130:
- /* CVTQL/V */
- case 0x530:
- /* CVTQL/SV */
+ case 0x030: /* CVTQL */
+ case 0x130: /* CVTQL/V */
+ case 0x530: /* CVTQL/SV */
REQUIRE_REG_31(ra);
- /* ??? I'm pretty sure there's nothing that /sv needs to do that
- /v doesn't do. The only thing I can think is that /sv is a
- valid instruction merely for completeness in the ISA. */
vc = dest_fpr(ctx, rc);
vb = load_fpr(ctx, rb);
- gen_helper_fcvtql_v_input(cpu_env, vb);
- gen_fcvtql(vc, vb);
+ gen_helper_cvtql(vc, cpu_env, vb);
+ gen_fp_exc_raise(rc, fn11);
break;
default:
goto invalid_opc;
--
1.9.3
- [Qemu-devel] [PULL for-2.1 00/18] target-alpha patch queue, Richard Henderson, 2014/07/10
- [Qemu-devel] [PULL 07/18] target-alpha: Fix cvttq vs large integers, Richard Henderson, 2014/07/09
- [Qemu-devel] [PULL 06/18] target-alpha: Raise IOV from CVTTQ, Richard Henderson, 2014/07/09
- [Qemu-devel] [PULL 08/18] target-alpha: Fix cvttq vs inf, Richard Henderson, 2014/07/09
- Re: [Qemu-devel] [PULL for-2.1 00/18] target-alpha patch queue, Peter Maydell, 2014/07/09
- [Qemu-devel] [PULL 10/18] target-alpha: Implement WH64EN, Richard Henderson, 2014/07/09
- [Qemu-devel] [PULL 04/18] target-alpha: Set fpcr_exc_status even for disabled exceptions, Richard Henderson, 2014/07/09
- [Qemu-devel] [PULL 02/18] target-alpha: Set PC correctly for floating-point exceptions, Richard Henderson, 2014/07/09
- [Qemu-devel] [PULL 16/18] target-alpha: Rename fcvtql, Richard Henderson, 2014/07/09
- [Qemu-devel] [PULL 15/18] target-alpha: Raise IOV from CVTQL,
Richard Henderson <=
- [Qemu-devel] [PULL 11/18] target-alpha: Disallow literal operand to 1C.30 to 1C.37, Richard Henderson, 2014/07/09
- [Qemu-devel] [PULL 17/18] target-alpha: Fix fpcr_flush_to_zero initialization, Richard Henderson, 2014/07/09
- [Qemu-devel] [PULL 18/18] target-alpha: Remove DNOD bit from FPCR, Richard Henderson, 2014/07/09
- [Qemu-devel] [PULL 09/18] target-alpha: Fix integer overflow checking insns, Richard Henderson, 2014/07/10
- [Qemu-devel] [PULL 05/18] target-alpha: Set EXC_M_SWC for exceptions from /S insns, Richard Henderson, 2014/07/10
- [Qemu-devel] [PULL 14/18] target-alpha: Suppress underflow from CVTTQ if DNZ, Richard Henderson, 2014/07/10
- [Qemu-devel] [PULL 13/18] target-alpha: Raise EXC_M_INV properly for fp inputs, Richard Henderson, 2014/07/10
- [Qemu-devel] [PULL 01/18] target-alpha: Forget installed round mode after MT_FPCR, Richard Henderson, 2014/07/10
- [Qemu-devel] [PULL 12/18] target-alpha: Ignore the unused fp_status exceptions, Richard Henderson, 2014/07/10
- [Qemu-devel] [PULL 03/18] target-alpha: Store IOV exception in fp_status, Richard Henderson, 2014/07/10