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[Qemu-devel] [PATCH 07/20] target-mips: add msa_reset(), global msa regi
From: |
Yongbok Kim |
Subject: |
[Qemu-devel] [PATCH 07/20] target-mips: add msa_reset(), global msa register |
Date: |
Mon, 14 Jul 2014 10:55:50 +0100 |
add msa_reset() and global msa register (d type only)
Signed-off-by: Yongbok Kim <address@hidden>
---
target-mips/translate.c | 74 ++++++++++++++++++++++++++++++++++++++++++
target-mips/translate_init.c | 45 +++++++++++++++++++++++++
2 files changed, 119 insertions(+), 0 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 6b4a82c..b8dbbdc 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1256,6 +1256,7 @@ static TCGv cpu_dspctrl, btarget, bcond;
static TCGv_i32 hflags;
static TCGv_i32 fpu_fcr0, fpu_fcr31;
static TCGv_i64 fpu_f64[32];
+static TCGv_i64 msa_wr_d[64];
static uint32_t gen_opc_hflags[OPC_BUF_SIZE];
static target_ulong gen_opc_btarget[OPC_BUF_SIZE];
@@ -1353,6 +1354,25 @@ static const char * const fregnames[] = {
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
};
+static const char * const msaregnames[] = {
+ "w0.d0", "w0.d1", "w1.d0", "w1.d1",
+ "w2.d0", "w2.d1", "w3.d0", "w3.d1",
+ "w4.d0", "w4.d1", "w4.d0", "w4.d1",
+ "w6.d0", "w6.d1", "w7.d0", "w7.d1",
+ "w8.d0", "w8.d1", "w9.d0", "w9.d1",
+ "w10.d0", "w10.d1", "w11.d0", "w11.d1",
+ "w12.d0", "w12.d1", "w13.d0", "w13.d1",
+ "w14.d0", "w14.d1", "w15.d0", "w15.d1",
+ "w16.d0", "w16.d1", "w17.d0", "w17.d1",
+ "w18.d0", "w18.d1", "w19.d0", "w19.d1",
+ "w20.d0", "w20.d1", "w21.d0", "w21.d1",
+ "w22.d0", "w22.d1", "w23.d0", "w23.d1",
+ "w24.d0", "w24.d1", "w25.d0", "w25.d1",
+ "w26.d0", "w26.d1", "w27.d0", "w27.d1",
+ "w28.d0", "w28.d1", "w29.d0", "w29.d1",
+ "w30.d0", "w30.d1", "w31.d0", "w31.d1",
+};
+
#define MIPS_DEBUG(fmt, ...) \
do { \
if (MIPS_DEBUG_DISAS) { \
@@ -14627,6 +14647,47 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx,
uint32_t op1, uint32_t op2,
/* End MIPSDSP functions. */
+/* MIPS SIMD Architecture (MSA) */
+
+static inline int check_msa_access(CPUMIPSState *env, DisasContext *ctx,
+ int wt, int ws, int wd)
+{
+ if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) &&
+ !(ctx->hflags & MIPS_HFLAG_F64))) {
+ generate_exception(ctx, EXCP_RI);
+ return 0;
+ }
+
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) {
+ if (ctx->insn_flags & ASE_MSA) {
+ generate_exception(ctx, EXCP_MSADIS);
+ return 0;
+ } else {
+ generate_exception(ctx, EXCP_RI);
+ return 0;
+ }
+ }
+
+ if (env->active_msa.msair & MSAIR_WRP_BIT) {
+ int curr_request = 0;
+ if (wd != -1) {
+ curr_request |= (1 << wd);
+ }
+ if (wt != -1) {
+ curr_request |= (1 << wt);
+ }
+ if (ws != -1) {
+ curr_request |= (1 << ws);
+ }
+ env->active_msa.msarequest = curr_request
+ & (~env->active_msa.msaaccess | env->active_msa.msasave);
+ if (unlikely(env->active_msa.msarequest != 0)) {
+ generate_exception(ctx, EXCP_MSADIS);
+ return 0;
+ }
+ }
+ return 1;
+}
static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
{
int32_t offset;
@@ -16119,6 +16180,15 @@ void mips_tcg_init(void)
fpu_f64[i] = tcg_global_mem_new_i64(TCG_AREG0, off, fregnames[i]);
}
+ for (i = 0; i < 32; i++) {
+ int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
+ msa_wr_d[i * 2] =
+ tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2]);
+ off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
+ msa_wr_d[i * 2 + 1] =
+ tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2 + 1]);
+ }
+
cpu_PC = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUMIPSState, active_tc.PC), "PC");
for (i = 0; i < MIPS_DSP_ACC; i++) {
@@ -16318,6 +16388,10 @@ void cpu_state_reset(CPUMIPSState *env)
}
}
#endif
+ /* MSA */
+ if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
+ msa_reset(env);
+ }
compute_hflags(env);
cs->exception_index = EXCP_NONE;
}
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 29dc2ef..9e0f67b 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -688,3 +688,48 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t
*def)
(0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
(0x1 << CP0MVPC1_PCP1);
}
+
+static void msa_reset(CPUMIPSState *env)
+{
+#ifdef CONFIG_USER_ONLY
+ /* MSA access enabled */
+ env->CP0_Config5 |= 1 << CP0C5_MSAEn;
+
+ /* DSP and CP1 enabled, 64-bit FPRs */
+ env->CP0_Status |= (1 << CP0St_MX);
+ env->hflags |= MIPS_HFLAG_DSP;
+
+ env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
+ env->hflags |= MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X;
+#endif
+
+ /* Vector register partitioning not implemented */
+ env->active_msa.msair = 0;
+ env->active_msa.msaaccess = 0xffffffff;
+ env->active_msa.msasave = 0;
+ env->active_msa.msarequest = 0;
+
+ /* MSA CSR:
+ - non-signaling floating point exception mode off (NX bit is 0)
+ - Cause, Enables, and Flags are all 0
+ - round to nearest / ties to even (RM bits are 0) */
+ env->active_msa.msacsr = 0;
+
+ /* tininess detected after rounding.*/
+ set_float_detect_tininess(float_tininess_after_rounding,
+ &env->active_msa.fp_status);
+
+ /* clear float_status exception flags */
+ set_float_exception_flags(0, &env->active_msa.fp_status);
+
+ /* set float_status rounding mode */
+ set_float_rounding_mode(float_round_nearest_even,
+ &env->active_msa.fp_status);
+
+ /* set float_status flush modes */
+ set_flush_to_zero(0, &env->active_msa.fp_status);
+ set_flush_inputs_to_zero(0, &env->active_msa.fp_status);
+
+ /* clear float_status nan mode */
+ set_default_nan_mode(0, &env->active_msa.fp_status);
+}
--
1.7.4
- [Qemu-devel] [PATCH 00/20] target-mips: add MSA module, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 01/20] target-mips: add MSA defines and data structure, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 05/20] target-mips: stop translation after ctc1, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 04/20] target-mips: add 8, 16, 32, 64 bits load and store, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 08/20] target-mips: add msa_helper.c, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 07/20] target-mips: add msa_reset(), global msa register,
Yongbok Kim <=
- [Qemu-devel] [PATCH 03/20] target-mips: move common funcs to cpu.h, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 09/20] target-mips: add MSA branch instructions, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 02/20] target-mips: add MSA exceptions, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 06/20] target-mips: add MSA opcode enum, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 10/20] target-mips: add MSA I8 format instructions, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 11/20] target-mips: add MSA I5 format instructions, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 12/20] target-mips: add MSA BIT format instructions, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 14/20] target-mips: add MSA ELM format instructions, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 16/20] target-mips: add MSA VEC/2R format instructions, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 18/20] target-mips: add MSA MI10 format instructions, Yongbok Kim, 2014/07/14