[Qemu-devel] [PATCH 0/6] target-mips: implement new MIPS64 Release 6 features

[Leon Alrae]

This patchset provides the following set of features:
- forbidden slot
- Config5.SBRI bit
- reserved fields and reserved registers (ignore write, read 0)
- updated MIPS64R6-generic CPU

It also includes modification of the behaviour when accessing unimplemented
CP0 register - the Reserved Instruction exception is not generated.

These changes should be applied on top of the two pending MIPS64R6 patchsets.

Thanks,
Leon

Leon Alrae (6):
  target-mips: add Config5.SBRI
  target-mips: implement forbidden slot
  target-mips: CP0_Status.CU0 no longer allows the user to access CP0
  target-mips: add restrictions for possible values in registers
  target-mips: correctly handle access to unimplemented CP0 register
  target-mips: enable features in MIPS64R6-generic CPU

 target-mips/cpu.h            |   17 +-
 target-mips/op_helper.c      |   63 +++-
 target-mips/translate.c      |  659 ++++++++++++++++++++++--------------------
 target-mips/translate_init.c |   11 +-
 4 files changed, 415 insertions(+), 335 deletions(-)

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1.7.5.4