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[Qemu-devel] [PATCH 3/6] target-mips: CP0_Status.CU0 no longer allows th
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PATCH 3/6] target-mips: CP0_Status.CU0 no longer allows the user to access CP0 |
Date: |
Mon, 14 Jul 2014 17:19:52 +0100 |
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/cpu.h | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index a35ab9d..b981ec7 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -789,7 +789,8 @@ static inline void compute_hflags(CPUMIPSState *env)
}
}
#endif
- if ((env->CP0_Status & (1 << CP0St_CU0)) ||
+ if (((env->CP0_Status & (1 << CP0St_CU0)) &&
+ !(env->insn_flags & ISA_MIPS32R6)) ||
!(env->hflags & MIPS_HFLAG_KSU)) {
env->hflags |= MIPS_HFLAG_CP0;
}
--
1.7.5.4
- [Qemu-devel] [PATCH 0/6] target-mips: implement new MIPS64 Release 6 features, Leon Alrae, 2014/07/14
- [Qemu-devel] [PATCH 1/6] target-mips: add Config5.SBRI, Leon Alrae, 2014/07/14
- [Qemu-devel] [PATCH 2/6] target-mips: implement forbidden slot, Leon Alrae, 2014/07/14
- [Qemu-devel] [PATCH 3/6] target-mips: CP0_Status.CU0 no longer allows the user to access CP0,
Leon Alrae <=
- [Qemu-devel] [PATCH 4/6] target-mips: add restrictions for possible values in registers, Leon Alrae, 2014/07/14
- [Qemu-devel] [PATCH 5/6] target-mips: correctly handle access to unimplemented CP0 register, Leon Alrae, 2014/07/14
- [Qemu-devel] [PATCH 6/6] target-mips: enable features in MIPS64R6-generic CPU, Leon Alrae, 2014/07/14