Re: [Qemu-devel] [PATCH v2 06/15] target-tricore: Add instructions of SRC opcode format

[Bastian Koppelmann]

> > +        tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
> Are you planning to come back to implement V and AV bits later?
Yes. I will do that in the next version of this patchset.
> > +    case OPC1_16_SRC_MOV_A:
> > +        /* load const4 again unsigned */
> > +        const4 = MASK_OP_SRC_CONST4(ctx->opcode);
> > +        tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
> Err.. I don't think this is right.  I see "signed" on page 3-224.
Well this seemed to have changed over the instructionset version. If you 
look at the implemented CPU TC1796 it uses version 1.3 and you refer to 
version 1.6. However there should be a mechanism like arm_feature to 
handle this.
> > +    case OPC1_16_SRC_SHA:
> > +        /* FIXME: const too long */
> > +        gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4, 4);
> > +        break;
> Huh?  Why the fixme?
>
>
> r~