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From: | Richard Henderson |
Subject: | Re: [Qemu-devel] [PATCH v2 07/15] target-tricore: Add instructions of SRR opcode format |
Date: | Tue, 15 Jul 2014 08:00:59 -0700 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 |
On 07/14/2014 10:41 AM, Bastian Koppelmann wrote: > + if ((arg & 0x80000000) | (arg & 0x40000000)) { \ > + env->PSW |= MASK_USB_AV; \ > + env->PSW |= MASK_USB_SAV; \ > + } else { \ > + env->PSW &= ~MASK_USB_AV; \ > + } \ The condition is wrong. It should be (arg ^ arg *2u) & 0x80000000 Although before you go too far down the road for representing PSW as a bitmask, consider splitting it apart into separate fields as we do on ARM. If you define S/AV as being bit 31 of two dedicated fields, then you don't even need the mask. You can do env->PSW_AV = arg ^ arg * 2u; env->PSW_SAV |= env->PSW_AV; which will most definitely be faster. Especially when you'll be wanting to inline that after most every arithmetic insn. r~
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