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[Qemu-devel] [PATCH v2 3/5] target-arm: A64: fix use 12 bit page tables
From: |
Alex Bennée |
Subject: |
[Qemu-devel] [PATCH v2 3/5] target-arm: A64: fix use 12 bit page tables for AArch64 |
Date: |
Wed, 30 Jul 2014 16:20:25 +0100 |
The AArch64 architecture only support 4k+ pages so using a smaller value
for QEMU's internal page table handling only makes us less efficient. I
ran some simple benchmarks and measured a 25-30% speed improvement for
CPU bound tasks like booting the kernel or compressing a section of a
file-system.
Signed-off-by: Alex Bennée <address@hidden>
---
v2:
- fix AArch64 references
- add benchmark notes to commit msg
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c83f249..83df513 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1051,11 +1051,18 @@ bool write_cpustate_to_list(ARMCPU *cpu);
#if defined(CONFIG_USER_ONLY)
#define TARGET_PAGE_BITS 12
#else
-/* The ARM MMU allows 1k pages. */
-/* ??? Linux doesn't actually use these, and they're deprecated in recent
- architecture revisions. Maybe a configure option to disable them. */
+#if defined(TARGET_AARCH64)
+/* You can't configure 1k pages on AArch64 hardware */
+#define TARGET_PAGE_BITS 12
+#else
+/* The ARM MMU allows 1k pages - although they are not used by Linux
+ * FIXME?: they're deprecated in recent architecture revisions and
+ * this does create a performance hit. Maybe a configure option to
+ * disable them?
+ */
#define TARGET_PAGE_BITS 10
#endif
+#endif
#if defined(TARGET_AARCH64)
# define TARGET_PHYS_ADDR_SPACE_BITS 48
--
2.0.3