[Qemu-devel] [PATCH v2 5/5] target-arm: A64: disable a bunch of ARMv5 machines

[Alex Bennée]

If you attempt to run a system image which uses 1k pages in the
qemu-system-aarch64 build it will fail thanks to the change to 12 bit
pages. The boards are still available for the qemu-system-arm build.

Signed-off-by: Alex Bennée <address@hidden>

diff --git a/default-configs/aarch64-softmmu.mak 
b/default-configs/aarch64-softmmu.mak
index 6d3b5c7..2bf26a0 100644
--- a/default-configs/aarch64-softmmu.mak
+++ b/default-configs/aarch64-softmmu.mak
@@ -1,6 +1,9 @@
 # Default configuration for aarch64-softmmu
 
-# We support all the 32 bit boards so need all their config
+# We support most of the 32 bit boards so need all their config
 include arm-softmmu.mak
 
+# we explicitly disable ones that require old ARMv5 support
+CONFIG_ARMV5_BOARDS=n
+
 # Currently no 64-bit specific config requirements
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index f10cc69..1e5656e 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -63,6 +63,7 @@ CONFIG_BITBANG_I2C=y
 CONFIG_FRAMEBUFFER=y
 CONFIG_XILINX_SPIPS=y
 
+CONFIG_ARMV5_BOARDS=y
 CONFIG_ARM11SCU=y
 CONFIG_A9SCU=y
 CONFIG_DIGIC=y
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 5899ed6..3dd87c6 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -1,8 +1,19 @@
-obj-y += boot.o collie.o exynos4_boards.o gumstix.o highbank.o
+obj-y += boot.o collie.o exynos4_boards.o
+obj-$(CONFIG_ARMV5_BOARDS) += gumstix.o
+obj-y += highbank.o
 obj-$(CONFIG_DIGIC) += digic_boards.o
-obj-y += integratorcp.o kzm.o mainstone.o musicpal.o nseries.o
-obj-y += omap_sx1.o palm.o ranchu.o realview.o spitz.o stellaris.o
-obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
+obj-$(CONFIG_ARMV5_BOARDS) += integratorcp.o
+obj-y += kzm.o
+obj-$(CONFIG_ARMV5_BOARDS) += mainstone.o
+obj-$(CONFIG_ARMV5_BOARDS) += musicpal.o
+obj-y += nseries.o
+obj-y += omap_sx1.o palm.o ranchu.o realview.o
+obj-$(CONFIG_ARMV5_BOARDS) += spitz.o
+obj-y += stellaris.o
+obj-$(CONFIG_ARMV5_BOARDS) += tosa.o
+obj-$(CONFIG_ARMV5_BOARDS) +=versatilepb.o
+obj-y += vexpress.o virt.o xilinx_zynq.o
+obj-$(CONFIG_ARMV5_BOARDS) +=z2.o
 obj-y += lionhead.o
 
 obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index 7e04e50..6152927 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -351,6 +351,7 @@ static void realview_init(QEMUMachineInitArgs *args,
     arm_load_kernel(ARM_CPU(first_cpu), &realview_binfo);
 }
 
+#ifndef TARGET_AARCH64
 static void realview_eb_init(QEMUMachineInitArgs *args)
 {
     if (!args->cpu_model) {
@@ -358,6 +359,7 @@ static void realview_eb_init(QEMUMachineInitArgs *args)
     }
     realview_init(args, BOARD_EB);
 }
+#endif
 
 static void realview_eb_mpcore_init(QEMUMachineInitArgs *args)
 {
@@ -383,12 +385,14 @@ static void realview_pbx_a9_init(QEMUMachineInitArgs 
*args)
     realview_init(args, BOARD_PBX_A9);
 }
 
+#ifndef TARGET_AARCH64
 static QEMUMachine realview_eb_machine = {
     .name = "realview-eb",
     .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
     .init = realview_eb_init,
     .block_default_type = IF_SCSI,
 };
+#endif
 
 static QEMUMachine realview_eb_mpcore_machine = {
     .name = "realview-eb-mpcore",
@@ -414,7 +418,9 @@ static QEMUMachine realview_pbx_a9_machine = {
 
 static void realview_machine_init(void)
 {
+#ifndef TARGET_AARCH64
     qemu_register_machine(&realview_eb_machine);
+#endif
     qemu_register_machine(&realview_eb_mpcore_machine);
     qemu_register_machine(&realview_pb_a8_machine);
     qemu_register_machine(&realview_pbx_a9_machine);
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 6c6f2b3..3c0ad9a 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -398,6 +398,7 @@ static ObjectClass *arm_cpu_class_by_name(const char 
*cpu_model)
 /* CPU models. These are not needed for the AArch64 linux-user build. */
 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 
+#ifndef TARGET_AARCH64
 static void arm926_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -452,6 +453,7 @@ static void arm1026_initfn(Object *obj)
         define_one_arm_cp_reg(cpu, &ifar);
     }
 }
+#endif /* TARGET_AARCH64 */
 
 static void arm1136_r2_initfn(Object *obj)
 {
@@ -780,6 +782,7 @@ static void cortex_a15_initfn(Object *obj)
     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 }
 
+#ifndef TARGET_AARCH64
 static void ti925t_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -947,6 +950,7 @@ static void pxa270c5_initfn(Object *obj)
     cpu->ctr = 0xd172172;
     cpu->reset_sctlr = 0x00000078;
 }
+#endif /* TARGET_AARCH64 */
 
 #ifdef CONFIG_USER_ONLY
 static void arm_any_initfn(Object *obj)
@@ -975,24 +979,16 @@ typedef struct ARMCPUInfo {
     void (*class_init)(ObjectClass *oc, void *data);
 } ARMCPUInfo;
 
+/* ARMv5 CPU models are disabled for the TARGET_AARCH64 build as they
+ * could potentially use the smaller 1k pages which we don't support
+ * for aarch64
+ */
 static const ARMCPUInfo arm_cpus[] = {
 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+#ifndef TARGET_AARCH64
     { .name = "arm926",      .initfn = arm926_initfn },
     { .name = "arm946",      .initfn = arm946_initfn },
     { .name = "arm1026",     .initfn = arm1026_initfn },
-    /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
-     * older core than plain "arm1136". In particular this does not
-     * have the v6K features.
-     */
-    { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
-    { .name = "arm1136",     .initfn = arm1136_initfn },
-    { .name = "arm1176",     .initfn = arm1176_initfn },
-    { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
-    { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
-                             .class_init = arm_v7m_class_init },
-    { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
-    { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
-    { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
     { .name = "ti925t",      .initfn = ti925t_initfn },
     { .name = "sa1100",      .initfn = sa1100_initfn },
     { .name = "sa1110",      .initfn = sa1110_initfn },
@@ -1009,6 +1005,20 @@ static const ARMCPUInfo arm_cpus[] = {
     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
+#endif
+    /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
+     * older core than plain "arm1136". In particular this does not
+     * have the v6K features.
+     */
+    { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
+    { .name = "arm1136",     .initfn = arm1136_initfn },
+    { .name = "arm1176",     .initfn = arm1176_initfn },
+    { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
+    { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
+                             .class_init = arm_v7m_class_init },
+    { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
+    { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
+    { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
 #ifdef CONFIG_USER_ONLY
     { .name = "any",         .initfn = arm_any_initfn },
 #endif
-- 
2.0.3