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Re: [Qemu-devel] [PATCH v2 0/5] AArch64 TLB performance improvements
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v2 0/5] AArch64 TLB performance improvements |
Date: |
Fri, 1 Aug 2014 23:26:20 +0100 |
On 1 August 2014 17:06, Peter Maydell <address@hidden> wrote:
> I'm taking the first two of these into target-arm.next because
> they're obvious standalone bugfixes. I need to think about the
> last three a bit more: I dislike just dropping the ARMv5 CPUs
> from qemu-system-aarch64, it's kind of arbitrary.
So:
* there's clearly a big perf win to be had here
* this patchset gives us that for 4K pages on AArch64
* but it doesn't help for 4K pages on AArch32 (really
common)
* and it's not going to be good for 64K pages on AArch64
either (which I suspect will not be a rare choice)
So I think it would be good if we investigated the degree
of difficulty in improving QEMU's TLB code so it isn't just
"one TLB entry size with larger pages a bolt-on which we
hope people don't actually use" first, before we just disable
all the v5 CPUs.
thanks
-- PMM