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Re: [Qemu-devel] [PATCH v3 15/15] target-tricore: Add instructions of SR


From: Richard Henderson
Subject: Re: [Qemu-devel] [PATCH v3 15/15] target-tricore: Add instructions of SR opcode format
Date: Mon, 04 Aug 2014 09:22:54 -1000
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.7.0

> +    case OPC2_16_SR_RSUB:
> +        /* overflow only if r1 = -0x80000000 */
> +        temp = tcg_const_i32(-0x80000000);
> +        t0 = tcg_const_i32(0);
> +        t1 = tcg_const_i32(1);
> +        tcg_gen_movcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp, t1, 
> t0);

This is setcond.

> +        tcg_gen_movcond_tl(TCG_COND_EQ, cpu_PSW_SV, cpu_gpr_d[r1], temp,
> +                           t1, cpu_PSW_SV);

This is or of the setcond.



r~



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