Re: [Qemu-devel] [PATCH v2 2/7] target-arm: Implement PMCCNTR_EL0 and related registers

[Peter Maydell]

On 18 August 2014 04:38, Peter Crosthwaite <address@hidden> wrote:
> On Sat, Aug 2, 2014 at 1:28 AM, Peter Maydell <address@hidden> wrote:
>> This is a pretty random order for the fields in a reginfo struct
>> (though existing code is not great here either).
>> Preferred is to put the .name first, then .state, then the
>> encoding in the same order as the v8 ARM ARM:
>>     .cp [if needed], .opc0, .opc1, .crn, .crm, .opc2
>> then .access and .accessfn
>> then .fieldoffset and .resetvalue, then read and writefns.
>>
>
> Done. I like the new scheme:
>
>  792     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
>  793       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12,.opc2 = 1,
>  794       .access = PL0_RW, .accessfn = pmreg_access,
>  795       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
> .resetvalue = 0,
>  796       .writefn = pmcntenset_write, .raw_writefn = raw_write },
>
> For completeness where does .type fit in?

After .access and .accessfn, I think. (There's also a fair amount
of existing code which puts it just before those two, which doesn't
look too awful, but after is slightly more logical.)

-- PMM