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[Qemu-devel] [PATCH target-arm v3 4/8] target-arm: Add arm_ccnt_enabled
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v3 4/8] target-arm: Add arm_ccnt_enabled function |
Date: |
Mon, 18 Aug 2014 01:14:06 -0700 |
From: Alistair Francis <address@hidden>
Include a helper function to determine if the CCNT counter
is enabled as well as the constants used to mask the pmccfiltr_el0
and c9_pmxevtyper registers.
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
---
Changed since v2 (PMM review):
Blank line for readability
Use switch instead of cascading ifs.
Use true and false.
Drop extraneous #endif #if
target-arm/helper.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 7363c8d..0318816 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -547,6 +547,50 @@ static CPAccessResult pmreg_access(CPUARMState *env, const
ARMCPRegInfo *ri)
}
#ifndef CONFIG_USER_ONLY
+
+#define PMCCFILTR_NSH 0x8000000
+#define PMCCFILTR_P 0x80000000
+#define PMCCFILTR_U 0x40000000
+
+#define PMXEVTYPER_P 0x80000000
+#define PMXEVTYPER_U 0x40000000
+
+static inline bool arm_ccnt_enabled(CPUARMState *env)
+{
+ /* This does not support checking for the secure/non-secure
+ * components of the PMCCFILTR_EL0 register
+ */
+
+ if (!(env->cp15.c9_pmcr & PMCRE)) {
+ return false;
+ }
+
+ switch (arm_current_pl(env)) {
+ case 2:
+ if (!(env->cp15.pmccfiltr_el0 & PMCCFILTR_NSH)) {
+ return false;
+ } else {
+ break;
+ }
+ case 1:
+ if (env->cp15.pmccfiltr_el0 & PMCCFILTR_P ||
+ env->cp15.c9_pmxevtyper & PMXEVTYPER_P) {
+ return false;
+ } else {
+ break;
+ }
+ case 0:
+ if (env->cp15.pmccfiltr_el0 & PMCCFILTR_U ||
+ env->cp15.c9_pmxevtyper & PMXEVTYPER_U) {
+ return false;
+ } else {
+ break;
+ }
+ }
+
+ return true;
+}
+
static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
--
2.0.1.1.gfbfc394
- [Qemu-devel] [PATCH target-arm v3 0/8] target-arm: Extend PMCCNTR for ARMv8, Peter Crosthwaite, 2014/08/18
- [Qemu-devel] [PATCH target-arm v3 1/8] target-arm: Make the ARM PMCCNTR register 64-bit, Peter Crosthwaite, 2014/08/18
- [Qemu-devel] [PATCH target-arm v3 2/8] arm: Implement PMCCNTR 32b read-modify-write, Peter Crosthwaite, 2014/08/18
- [Qemu-devel] [PATCH target-arm v3 3/8] target-arm: Implement PMCCNTR_EL0 and related registers, Peter Crosthwaite, 2014/08/18
- [Qemu-devel] [PATCH target-arm v3 4/8] target-arm: Add arm_ccnt_enabled function,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH target-arm v3 5/8] target-arm: Implement pmccntr_sync function, Peter Crosthwaite, 2014/08/18
- [Qemu-devel] [PATCH target-arm v3 6/8] target-arm: Remove old code and replace with new functions, Peter Crosthwaite, 2014/08/18
- [Qemu-devel] [PATCH target-arm v3 7/8] target-arm: Implement pmccfiltr_write function, Peter Crosthwaite, 2014/08/18
- [Qemu-devel] [PATCH target-arm v3 8/8] target-arm: Call pmccntr_sync() when swapping ELs, Peter Crosthwaite, 2014/08/18