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[Qemu-devel] [PATCH v6 09/15] target-tricore: Add instructions of SRRS a
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH v6 09/15] target-tricore: Add instructions of SRRS and SLRO opcode format |
Date: |
Fri, 22 Aug 2014 17:52:30 +0100 |
Add instructions of SSRS and SLRO opcode format.
Add micro-op generator functions for offset loads.
Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-tricore/translate.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 9ba90c4..64ad4ec 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -107,6 +107,26 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f,
* Functions to generate micro-ops
*/
+/* Functions for load/save to/from memory */
+
+static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
+ int16_t con, TCGMemOp mop)
+{
+ TCGv temp = tcg_temp_new();
+ tcg_gen_addi_tl(temp, r2, con);
+ tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
+ tcg_temp_free(temp);
+}
+
+static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
+ int16_t con, TCGMemOp mop)
+{
+ TCGv temp = tcg_temp_new();
+ tcg_gen_addi_tl(temp, r2, con);
+ tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
+ tcg_temp_free(temp);
+}
+
/* Functions for arithmetic instructions */
static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
@@ -513,9 +533,17 @@ static void decode_ssr_opc(DisasContext *ctx, int op1)
static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
{
int op1;
+ int r1, r2;
+ int32_t const16;
+ TCGv temp;
op1 = MASK_OP_MAJOR(ctx->opcode);
+ /* handle ADDSC.A opcode only being 6 bit long */
+ if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) {
+ op1 = OPC1_16_SRRS_ADDSC_A;
+ }
+
switch (op1) {
case OPC1_16_SRC_ADD:
case OPC1_16_SRC_ADD_A15:
@@ -568,6 +596,37 @@ static void decode_16Bit_opc(CPUTRICOREState *env,
DisasContext *ctx)
case OPC1_16_SSR_ST_W_POSTINC:
decode_ssr_opc(ctx, op1);
break;
+/* SRRS-format */
+ case OPC1_16_SRRS_ADDSC_A:
+ r2 = MASK_OP_SRRS_S2(ctx->opcode);
+ r1 = MASK_OP_SRRS_S1D(ctx->opcode);
+ const16 = MASK_OP_SRRS_N(ctx->opcode);
+ temp = tcg_temp_new();
+ tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
+ tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
+ tcg_temp_free(temp);
+ break;
+/* SLRO-format */
+ case OPC1_16_SLRO_LD_A:
+ r1 = MASK_OP_SLRO_D(ctx->opcode);
+ const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
+ gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
+ break;
+ case OPC1_16_SLRO_LD_BU:
+ r1 = MASK_OP_SLRO_D(ctx->opcode);
+ const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
+ gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
+ break;
+ case OPC1_16_SLRO_LD_H:
+ r1 = MASK_OP_SLRO_D(ctx->opcode);
+ const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
+ gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
+ break;
+ case OPC1_16_SLRO_LD_W:
+ r1 = MASK_OP_SLRO_D(ctx->opcode);
+ const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
+ gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
+ break;
}
}
--
2.1.0
- [Qemu-devel] [PATCH v6 00/15] TriCore architecture guest implementation, Bastian Koppelmann, 2014/08/22
- [Qemu-devel] [PATCH v6 01/15] target-tricore: Add target stubs and qom-cpu, Bastian Koppelmann, 2014/08/22
- [Qemu-devel] [PATCH v6 04/15] target-tricore: Add initialization for translation and activate target, Bastian Koppelmann, 2014/08/22
- [Qemu-devel] [PATCH v6 02/15] target-tricore: Add board for systemmode, Bastian Koppelmann, 2014/08/22
- [Qemu-devel] [PATCH v6 03/15] target-tricore: Add softmmu support, Bastian Koppelmann, 2014/08/22
- [Qemu-devel] [PATCH v6 05/15] target-tricore: Add masks and opcodes for decoding, Bastian Koppelmann, 2014/08/22
- [Qemu-devel] [PATCH v6 06/15] target-tricore: Add instructions of SRC opcode format, Bastian Koppelmann, 2014/08/22
- [Qemu-devel] [PATCH v6 07/15] target-tricore: Add instructions of SRR opcode format, Bastian Koppelmann, 2014/08/22
- [Qemu-devel] [PATCH v6 08/15] target-tricore: Add instructions of SSR opcode format, Bastian Koppelmann, 2014/08/22
- [Qemu-devel] [PATCH v6 09/15] target-tricore: Add instructions of SRRS and SLRO opcode format,
Bastian Koppelmann <=
- [Qemu-devel] [PATCH v6 13/15] target-tricore: Add instructions of SC opcode format, Bastian Koppelmann, 2014/08/22
- [Qemu-devel] [PATCH v6 14/15] target-tricore: Add instructions of SLR, SSRO and SRO opcode format, Bastian Koppelmann, 2014/08/22
- [Qemu-devel] [PATCH v6 10/15] target-tricore: Add instructions of SB opcode format, Bastian Koppelmann, 2014/08/22
- [Qemu-devel] [PATCH v6 11/15] target-tricore: Add instructions of SBC and SBRN opcode format, Bastian Koppelmann, 2014/08/22
- [Qemu-devel] [PATCH v6 12/15] target-tricore: Add instructions of SBR opcode format, Bastian Koppelmann, 2014/08/22
- [Qemu-devel] [PATCH v6 15/15] target-tricore: Add instructions of SR opcode format, Bastian Koppelmann, 2014/08/22