[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] pert stat in KVM guest can not get LLC-loads hardware c
From: |
Liang, Kan |
Subject: |
Re: [Qemu-devel] pert stat in KVM guest can not get LLC-loads hardware cache event |
Date: |
Wed, 27 Aug 2014 19:35:26 +0000 |
> > Inside the guest, I am using "perf stat -e dTLB-load-misses -e
> > dTLB-loads -e L1-dcache-loads -e L1-dcache-load-misses -e
> > L1-dcache-prefetch-misses ", followed by the parsec command.
> >
The misses/hit radio is the first number after "#".
For your case, 0.00% is the misses/hit radio for dTLB cache.
0.74% is the misses/hit radio for L1dcache.
I have no idea what does 80.00% mean.
> >
> > On Wed, Aug 27, 2014 at 12:28 PM, Liang, Kan <address@hidden> wrote:
> > >
> > >> > Hi, Kan,
> > >> >
> > >> > The dTLB-load-misses is 0, but it shows 80.00%hit, does that mean
> > >> > the
> > >> > TLB- load miss is 0.8 * (dTLB-loads). Thanks.
> > >> >
> > >> >
> > >> > 0 dTLB-load-misses # 0.00% of all dTLB
> > >> > cache hits [80.00%]
> > >> >
> > >> > 782,565,273,315 dTLB-loads
> > >> > [80.00%]
> > >> >
> > >> > 782,552,911,616 L1-dcache-loads
> > >> > [80.00%]
> > >> >
> > >> > 5,810,697,456 L1-dcache-load-misses # 0.74% of all
> > >> > L1-dcache hits [80.00%]
> > >> >
> > >> > 2,145,907,209 L1-dcache-prefetch-misses
> > >> > [80.00%]
> > >> >
> > >> > - Hui
- [Qemu-devel] pert stat in KVM guest can not get LLC-loads hardware cache event, Steven, 2014/08/27
- Message not available
- Re: [Qemu-devel] pert stat in KVM guest can not get LLC-loads hardware cache event, Steven, 2014/08/27
- Re: [Qemu-devel] pert stat in KVM guest can not get LLC-loads hardware cache event, Steven, 2014/08/27
- Message not available
- Re: [Qemu-devel] pert stat in KVM guest can not get LLC-loads hardware cache event, Liang, Kan, 2014/08/27
- Re: [Qemu-devel] pert stat in KVM guest can not get LLC-loads hardware cache event, Steven, 2014/08/27
- Message not available
- Re: [Qemu-devel] pert stat in KVM guest can not get LLC-loads hardware cache event,
Liang, Kan <=