Re: [Qemu-devel] [PATCH v4 00/33] target-arm: add Security Extensions for CPUs

[Peter Maydell]

On 1 July 2014 00:09,  <address@hidden> wrote:
> From: Greg Bellows <address@hidden>
>
> Updated Fabian's v3 patchset for review comments.  This patchset includes
> changes in support of the security extension on v7 aarch32 with hooks for 
> later
> enabling v8 aarch64.
>
> The patches are built upon and therefore dependent on v3 of Xilinx's second 
> round of EL2/3 patches.

Just a quick summary of what I think are the
"big picture" issues we still need to resolve:

1. how do we implement the S/NS attribute on memory accesses ?
   (I wrote up a suggestion for this and sent it out yesterday;
   we don't need to actually implement this prior to merging
   the other code if guests don't rely on it in practice)
2. what is our approach for maintaining backward compatibility
   with existing guests that expect to start in EL1 and/or
   without trustzone (or for determining that there isn't
   a serious back-compat problem) ?
3. how does this fit in with KVM (where we must start
   the guest in NS-EL1 / NS-SVC) ?
4. what are the right set of functions and concepts for
   current EL/current PL/S vs NS, given the differences
   between AArch32 and AArch64 here (for 32 bit the
   Secure Monitor and Secure PL1 are at the same privilege
   level; for 64 bit they're EL3 and EL1) ?

I'll try to dig in a bit more and formulate an opinion
about 2-4 next week.

thanks
-- PMM