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Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] Enabling floating point instruct
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From: |
Alexander Graf |
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Subject: |
Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs |
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Date: |
Wed, 10 Sep 2014 11:20:14 +0200 |
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User-agent: |
Mozilla/5.0 (Macintosh; Intel Mac OS X 10.9; rv:31.0) Gecko/20100101 Thunderbird/31.1.0 |
On 10.09.14 07:03, Pierre Mallard wrote:
> This patch series enable floating point instruction in 440x5 CPUs
> which have the capabilities to have optional APU FPU.
>
> 1) Add floating point standard insns flag to 440x5 in case there is an apu
> fpu.
> 2) Define a new floating point insns flag for operation
> previously reserved to 64 bits proc (fcfid, fctid, fctidz)
> 3) Apply this new flag to fcfid, fctid, fctidz and move TARGET_PPC64
> restrictions
I've looked through the patches mostly from a stylistic point of view.
As for whether the changes are technically correct and fully adhere to
the specs, I haven't verified anything and would leave that part to Tom :).
Alex