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Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] Enabling floating point instruct
From: |
Tom Musta |
Subject: |
Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs |
Date: |
Wed, 10 Sep 2014 12:15:46 -0500 |
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Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 |
On 9/10/2014 4:20 AM, Alexander Graf wrote:
>
>
> On 10.09.14 07:03, Pierre Mallard wrote:
>> This patch series enable floating point instruction in 440x5 CPUs
>> which have the capabilities to have optional APU FPU.
>>
>> 1) Add floating point standard insns flag to 440x5 in case there is an apu
>> fpu.
>> 2) Define a new floating point insns flag for operation
>> previously reserved to 64 bits proc (fcfid, fctid, fctidz)
>> 3) Apply this new flag to fcfid, fctid, fctidz and move TARGET_PPC64
>> restrictions
>
> I've looked through the patches mostly from a stylistic point of view.
> As for whether the changes are technically correct and fully adhere to
> the specs, I haven't verified anything and would leave that part to Tom :).
>
I went back to some old (paper) versions of the ISA circa 1998 and the Floating
Convert To/From Doubleword instructions all have this clause:
"This instruction is defined only for 64-bit implementations. Using it on a
32-bit implementation will cause the system illegal instruction error handler
to be invoked."
I believe this view of things was in play for the 60x and PowerMAC era 32-bit
CPUs. Which is consistent with the existing QEMU implementation.
The next revision of the spec that I have is Power ISA 2.03 (2006) and the
clause is gone. Furthermore, the instructions are *NOT* in the "64" category.
To complicate matters more, the unsigned integer versions were added in ISA
2.06 (fcfidu, fctidu, fctiduz). QEMU deals with these via the
PPC2_FP_CVT_ISA206 flag.
My interpretation is that all of the fc[tf]id[*] instructions are a required
part of any Power floating point implementation -- 32-bit or 64-bit is
irrelevant.
Based on all of this, I think it would make sense to do the following in this
patch series:
(1) Eliminate the TARGET_PPC64 checks for all six FP Doubleword Integer
Conversion instructions.
(2) Defined a new flag for FP Signed Doubleword Conversion instructions
(PPC2_FP_CVT_S64). Use this flag exclusively when defining the opcode tables,
e.g.
+/* fctidz */
+GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
(3) You would have to add the flag to all existing 64-bit CPUs that support
floating point. And of course, to your new 440-w-fpu CPU.
- [Qemu-devel] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs, Pierre Mallard, 2014/09/10
- [Qemu-devel] [PATCH 1/3] target-ppc : Add floating point ability to 440x5 PPC CPU, Pierre Mallard, 2014/09/10
- [Qemu-devel] [PATCH 2/3] target-ppc : Add PPC_FLOAT_64 flag to instructions type, Pierre Mallard, 2014/09/10
- [Qemu-devel] [PATCH 3/3] target-ppc : Add PPC_FLOAT_64 type to fctid, fctidz and fcfid and remove their TARGET_PPC64 restriction, Pierre Mallard, 2014/09/10
- Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs, Alexander Graf, 2014/09/10
- Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs,
Tom Musta <=