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[Qemu-devel] [PATCH v5 00/33] target-arm: add Security Extensions for CP
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v5 00/33] target-arm: add Security Extensions for CPUs |
Date: |
Tue, 30 Sep 2014 16:49:12 -0500 |
Version 5 of the ARM processor security extension (TrustZone) support.
This patchset includes changes to support the processor security extensions
on ARMv7 aarch32 with hooks for later enabling v8 aarch64/32.
Summary of changes from v4 -> v5:
- Renamed arm_current_pl to arm_current_el
- Added banked MAIR support
- Added gdb SCR register
- Bugfixes and clean-up
- Reordered patches so infrastructure happens before use.
More detailed change history included on a per-patch basis.
Fabian Aggeler (27):
target-arm: increase arrays of registers R13 & R14
target-arm: add arm_is_secure() function
target-arm: make arm_current_pl() return PL3
target-arm: A32: Emulate the SMC instruction
target-arm: extend async excp masking
target-arm: add async excp target_el function
target-arm: add macros to access banked registers
target-arm: arrayfying fieldoffset for banking
target-arm: insert Aarch32 cpregs twice into hashtable
target-arm: move Aarch32 SCR into security reglist
target-arm: implement IRQ/FIQ routing to Monitor mode
target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI
target-arm: add NSACR register
target-arm: add MVBAR support
target-arm: add SCTLR_EL3 and make SCTLR banked
target-arm: make CSSELR banked
target-arm: add TTBR0_EL3 and make TTBR0/1 banked
target-arm: add TCR_EL3 and make TTBCR banked
target-arm: make c2_mask and c2_base_mask banked
target-arm: make DACR banked
target-arm: make IFSR banked
target-arm: make DFSR banked
target-arm: make IFAR/DFAR banked
target-arm: make PAR banked
target-arm: make VBAR banked
target-arm: make c13 cp regs banked (FCSEIDR, ...)
target-arm: add cpu feature EL3 to CPUs with Security Extensions
Greg Bellows (3):
target-arm: rename arm_current_pl to arm_current_el
target-arm: make MAIR0/1 banked
target-arm: add GDB scr register
Sergey Fedorov (3):
target-arm: reject switching to monitor mode
target-arm: add non-secure Translation Block flag
target-arm: add SDER definition
gdb-xml/arm-core.xml | 1 +
hw/arm/pxa2xx.c | 4 +-
target-arm/cpu.c | 13 +-
target-arm/cpu.h | 471 +++++++++++++++++++++++----
target-arm/gdbstub.c | 3 +
target-arm/helper-a64.c | 6 +-
target-arm/helper.c | 772 ++++++++++++++++++++++++++++++++++-----------
target-arm/internals.h | 11 +-
target-arm/machine.c | 4 +-
target-arm/op_helper.c | 19 +-
target-arm/translate-a64.c | 3 +-
target-arm/translate.c | 56 +++-
target-arm/translate.h | 1 +
13 files changed, 1092 insertions(+), 272 deletions(-)
--
1.8.3.2
- [Qemu-devel] [PATCH v5 00/33] target-arm: add Security Extensions for CPUs,
Greg Bellows <=
- [Qemu-devel] [PATCH v5 03/33] target-arm: reject switching to monitor mode, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 05/33] target-arm: make arm_current_pl() return PL3, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 01/33] target-arm: increase arrays of registers R13 & R14, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 04/33] target-arm: rename arm_current_pl to arm_current_el, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 02/33] target-arm: add arm_is_secure() function, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 07/33] target-arm: extend async excp masking, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 08/33] target-arm: add async excp target_el function, Greg Bellows, 2014/09/30