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[Qemu-devel] [PATCH v5 20/33] target-arm: make CSSELR banked
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v5 20/33] target-arm: make CSSELR banked |
Date: |
Tue, 30 Sep 2014 16:49:32 -0500 |
From: Fabian Aggeler <address@hidden>
Rename CSSELR (cache size selection register) and add secure
instance (Aarch32).
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
----------
v4 -> v5
- Changed to use the CCSIDR cpreg bank flag to select the csselr bank instead
of the A32_BANKED macro. This more accurately uses the secure state bank
matching the CCSIDR.
---
target-arm/cpu.h | 10 +++++++++-
target-arm/helper.c | 22 +++++++++++++++++-----
2 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 44d7098..332a2cb 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -177,7 +177,15 @@ typedef struct CPUARMState {
/* System control coprocessor (cp15) */
struct {
uint32_t c0_cpuid;
- uint64_t c0_cssel; /* Cache size selection. */
+ union { /* Cache size selection */
+ struct {
+ uint64_t csselr_ns;
+ uint64_t csselr_s;
+ };
+ struct {
+ uint64_t csselr_el1;
+ };
+ };
union { /* System control register. */
struct {
uint64_t sctlr_ns;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 7d26acc..90f5352 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -789,7 +789,14 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo
*ri, uint64_t value)
static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
ARMCPU *cpu = arm_env_get_cpu(env);
- return cpu->ccsidr[env->cp15.c0_cssel];
+
+ /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
+ * bank
+ */
+ uint32_t index = A32_BANKED_REG_GET(env, csselr,
+ (ri->type & ARM_CP_BANK_S) == ARM_CP_BANK_S);
+
+ return cpu->ccsidr[index];
}
static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -914,10 +921,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
{ .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
.access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
- { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
- .writefn = csselr_write, .resetvalue = 0 },
+ { .name = "CSSELR",
+ .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
+ .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
+ .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
+ offsetof(CPUARMState, cp15.csselr_el1) } },
/* Auxiliary ID register: this actually has an IMPDEF value but for now
* just RAZ for all cores:
*/
@@ -2270,6 +2278,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
.type = ARM_CP_NO_MIGRATE,
.access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
+ { .name = "CSSELR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
+ .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.csselr_el1) },
REGINFO_SENTINEL
};
--
1.8.3.2
- [Qemu-devel] [PATCH v5 10/33] target-arm: add non-secure Translation Block flag, (continued)
- [Qemu-devel] [PATCH v5 10/33] target-arm: add non-secure Translation Block flag, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 06/33] target-arm: A32: Emulate the SMC instruction, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 11/33] target-arm: arrayfying fieldoffset for banking, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 09/33] target-arm: add macros to access banked registers, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 12/33] target-arm: insert Aarch32 cpregs twice into hashtable, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 13/33] target-arm: move Aarch32 SCR into security reglist, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 14/33] target-arm: implement IRQ/FIQ routing to Monitor mode, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 16/33] target-arm: add NSACR register, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 17/33] target-arm: add SDER definition, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 15/33] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 20/33] target-arm: make CSSELR banked,
Greg Bellows <=
- [Qemu-devel] [PATCH v5 19/33] target-arm: add SCTLR_EL3 and make SCTLR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 18/33] target-arm: add MVBAR support, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 21/33] target-arm: add TTBR0_EL3 and make TTBR0/1 banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 24/33] target-arm: make DACR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 23/33] target-arm: make c2_mask and c2_base_mask banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 27/33] target-arm: make IFAR/DFAR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 30/33] target-arm: make MAIR0/1 banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 28/33] target-arm: make PAR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 33/33] target-arm: add cpu feature EL3 to CPUs with Security Extensions, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 25/33] target-arm: make IFSR banked, Greg Bellows, 2014/09/30