[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v5 13/33] target-arm: move Aarch32 SCR into security
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v5 13/33] target-arm: move Aarch32 SCR into security reglist |
Date: |
Tue, 30 Sep 2014 16:49:25 -0500 |
From: Fabian Aggeler <address@hidden>
Define a new ARM CP register info list for the ARMv7 Security Extension
feature. Register that list only for ARM cores with Security Extension/EL3
support. Moving Aarch32 SCR into Security Extension register group.
Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
------------------
v4 -> v5
- Added reset value on SCR_EL3
- Squashed SCR Migration fix (previously patch 33)
This patch adds code to mark duplicate CP register registrations as
NO_MIGRATE to avoid duplicate migrations.
v3 -> v4
- Renamed security_cp_reginfo to v7_el3_cp_reginfo
- Conditionalized define on whether v7 or v8 were enabled
Signed-off-by: Greg Bellows <address@hidden>
---
target-arm/helper.c | 26 +++++++++++++++++++-------
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index a0f53dd..cb2eb3c 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -898,9 +898,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.access = PL1_RW, .writefn = vbar_write,
.fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
.resetvalue = 0 },
- { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetoflow32(CPUARMState,
cp15.scr_el3),
- .resetvalue = 0, .writefn = scr_write },
{ .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
.access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
@@ -2335,11 +2332,21 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
.access = PL3_RW, .writefn = vbar_write,
.fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
.resetvalue = 0 },
- { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
- .type = ARM_CP_NO_MIGRATE,
+ /* SCR will always be registered for v7, but not necessarily for v8, so
+ * this entry is marked to allow migration to be handled by the v7
+ * registration instance.
+ */
+ { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
- .writefn = scr_write },
+ .resetvalue = 0, .writefn = scr_write },
+ REGINFO_SENTINEL
+};
+
+static const ARMCPRegInfo v7_el3_cp_reginfo[] = {
+ { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
+ .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
+ .resetvalue = 0, .writefn = scr_write},
REGINFO_SENTINEL
};
@@ -2960,7 +2967,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
}
if (arm_feature(env, ARM_FEATURE_EL3)) {
- define_arm_cp_regs(cpu, v8_el3_cp_reginfo);
+ if (arm_feature(env, ARM_FEATURE_V8)) {
+ define_arm_cp_regs(cpu, v8_el3_cp_reginfo);
+ }
+ if (arm_feature(env, ARM_FEATURE_V7)) {
+ define_arm_cp_regs(cpu, v7_el3_cp_reginfo);
+ }
}
if (arm_feature(env, ARM_FEATURE_MPU)) {
/* These are the MPU registers prior to PMSAv6. Any new
--
1.8.3.2
- [Qemu-devel] [PATCH v5 01/33] target-arm: increase arrays of registers R13 & R14, (continued)
- [Qemu-devel] [PATCH v5 01/33] target-arm: increase arrays of registers R13 & R14, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 04/33] target-arm: rename arm_current_pl to arm_current_el, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 02/33] target-arm: add arm_is_secure() function, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 07/33] target-arm: extend async excp masking, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 08/33] target-arm: add async excp target_el function, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 10/33] target-arm: add non-secure Translation Block flag, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 06/33] target-arm: A32: Emulate the SMC instruction, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 11/33] target-arm: arrayfying fieldoffset for banking, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 09/33] target-arm: add macros to access banked registers, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 12/33] target-arm: insert Aarch32 cpregs twice into hashtable, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 13/33] target-arm: move Aarch32 SCR into security reglist,
Greg Bellows <=
- [Qemu-devel] [PATCH v5 14/33] target-arm: implement IRQ/FIQ routing to Monitor mode, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 16/33] target-arm: add NSACR register, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 17/33] target-arm: add SDER definition, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 15/33] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 20/33] target-arm: make CSSELR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 19/33] target-arm: add SCTLR_EL3 and make SCTLR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 18/33] target-arm: add MVBAR support, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 21/33] target-arm: add TTBR0_EL3 and make TTBR0/1 banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 24/33] target-arm: make DACR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 23/33] target-arm: make c2_mask and c2_base_mask banked, Greg Bellows, 2014/09/30