Re: [Qemu-devel] [PATCH v4 21/21] target-mips: define a new generic CPU supporting MIPS64 Release 6 ISA

[Yongbok Kim]

As this point all new R6 instructions is available,
this patch should be good enough to make it able to test especially for 
R6 Linux user mode binaries.

Reviewed-by: Yongbok Kim <address@hidden>

Regards,
Yongbok


On 08/10/2014 11:55, Leon Alrae wrote:
> Signed-off-by: Leon Alrae <address@hidden>
> ---
> v3:
> * add comment to make it clear that the current definition of MIPS64R6-generic
>    CPU does not contain support for all MIPS64R6 features yet.
> ---
>   target-mips/translate_init.c | 30 ++++++++++++++++++++++++++++++
>   1 file changed, 30 insertions(+)
>
> diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
> index 29dc2ef..67b7837 100644
> --- a/target-mips/translate_init.c
> +++ b/target-mips/translate_init.c
> @@ -516,6 +516,36 @@ static const mips_def_t mips_defs[] =
>           .mmu_type = MMU_TYPE_R4000,
>       },
>       {
> +        /* A generic CPU supporting MIPS64 Release 6 ISA.
> +           FIXME: It does not support all the MIPS64R6 features yet.
> +                  Eventually this should be replaced by a real CPU model. */
> +        .name = "MIPS64R6-generic",
> +        .CP0_PRid = 0x00010000,
> +        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
> +                       (MMU_TYPE_R4000 << CP0C0_MT),
> +        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
> +                       (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
> +                       (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
> +                       (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
> +        .CP0_Config2 = MIPS_CONFIG2,
> +        .CP0_Config3 = MIPS_CONFIG3,
> +        .CP0_LLAddr_rw_bitmask = 0,
> +        .CP0_LLAddr_shift = 0,
> +        .SYNCI_Step = 32,
> +        .CCRes = 2,
> +        .CP0_Status_rw_bitmask = 0x30D8FFFF,
> +        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
> +                    (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) |
> +                    (0x0 << FCR0_REV),
> +        .SEGBITS = 42,
> +        /* The architectural limit is 59, but we have hardcoded 36 bit
> +           in some places...
> +        .PABITS = 59, */ /* the architectural limit */
> +        .PABITS = 36,
> +        .insn_flags = CPU_MIPS64R6,
> +        .mmu_type = MMU_TYPE_R4000,
> +    },
> +    {
>           .name = "Loongson-2E",
>           .CP0_PRid = 0x6302,
>           /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/