Re: [Qemu-devel] [PATCH v2 1/9] target-mips: add KScratch registers

[Yongbok Kim]

Not related code changes are included.
See the comment below.

Other than,
Reviewed-by: Yongbok Kim <address@hidden>

Regards,
Yongbok


On 08/07/2014 08:57, Leon Alrae wrote:
> KScratch<n> Registers (CP0 Register 31, Selects 2 to 7)
>
> The KScratch registers are read/write registers available for scratch pad
> storage by kernel mode software. They are 32-bits in width for 32-bit
> processors and 64-bits for 64-bit processors.
>
> CP0Config4.KScrExist[2:7] bits indicate presence of CP0_KScratch1-6 registers.
> For Release 6, all KScratch registers are required.
>
> Signed-off-by: Leon Alrae <address@hidden>
> ---
>   target-mips/cpu.h       |    3 +++
>   target-mips/translate.c |   44 ++++++++++++++++++++++++++++++++++++++++++++
>   2 files changed, 47 insertions(+), 0 deletions(-)
>
> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> index 51a8331..4f6aa5b 100644
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -136,6 +136,7 @@ typedef struct mips_def_t mips_def_t;
>   #define MIPS_TC_MAX 5
>   #define MIPS_FPU_MAX 1
>   #define MIPS_DSP_ACC 4
> +#define MIPS_KSCRATCH_NUM 6
>   
>   typedef struct TCState TCState;
>   struct TCState {
> @@ -229,6 +230,7 @@ struct CPUMIPSState {
>       target_ulong CP0_EntryLo0;
>       target_ulong CP0_EntryLo1;
>       target_ulong CP0_Context;
> +    target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
>       int32_t CP0_PageMask;
>       int32_t CP0_PageGrain;
>       int32_t CP0_Wired;
> @@ -375,6 +377,7 @@ struct CPUMIPSState {
>       uint32_t CP0_Config4;
>       uint32_t CP0_Config4_rw_bitmask;
>   #define CP0C4_M    31
> +#define CP0C4_KScrExist 16
>       uint32_t CP0_Config5;
>       uint32_t CP0_Config5_rw_bitmask;
>   #define CP0C5_M          31
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 6956fdd..ee18bf3 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -1175,6 +1175,7 @@ typedef struct DisasContext {
>       int bstate;
>       target_ulong btarget;
>       bool ulri;
> +    int kscrexist;
>   } DisasContext;
>   
>   enum {
> @@ -4611,6 +4612,15 @@ static inline void gen_mtc0_store64 (TCGv arg, 
> target_ulong off)
>       tcg_gen_st_tl(arg, cpu_env, off);
>   }
>   
> +static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg)
> +{
> +    if (ctx->insn_flags & ISA_MIPS32R6) {
> +        tcg_gen_movi_tl(arg, 0);
> +    } else {
> +        tcg_gen_movi_tl(arg, ~0);
> +    }
> +}
> +

Not related with KScratch registers. It would be better to be a separate 
patch or
as part of the patch [PATCH 5/6] target-mips: correctly handle access to 
unimplemented CP0 register.

>   static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
>   {
>       const char *rn = "invalid";
> @@ -5193,6 +5203,16 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int 
> reg, int sel)
>               gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
>               rn = "DESAVE";
>               break;
> +        case 2 ... 7:
> +            if (ctx->kscrexist & (1 << sel)) {
> +                tcg_gen_ld_tl(arg, cpu_env,
> +                              offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
> +                tcg_gen_ext32s_tl(arg, arg);
> +                rn = "KScratch";
> +            } else {
> +                gen_mfc0_unimplemented(ctx, arg);
> +            }
> +            break;
>           default:
>               goto die;
>           }
> @@ -5801,6 +5821,13 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int 
> reg, int sel)
>               gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
>               rn = "DESAVE";
>               break;
> +        case 2 ... 7:
> +            if (ctx->kscrexist & (1 << sel)) {
> +                tcg_gen_st_tl(arg, cpu_env,
> +                              offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
> +                rn = "KScratch";
> +            }
> +            break;
>           default:
>               goto die;
>           }
> @@ -6388,6 +6415,15 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int 
> reg, int sel)
>               gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
>               rn = "DESAVE";
>               break;
> +        case 2 ... 7:
> +            if (ctx->kscrexist & (1 << sel)) {
> +                tcg_gen_ld_tl(arg, cpu_env,
> +                              offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
> +                rn = "KScratch";
> +            } else {
> +                gen_mfc0_unimplemented(ctx, arg);
> +            }
> +            break;
>           default:
>               goto die;
>           }
> @@ -6987,6 +7023,13 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int 
> reg, int sel)
>               gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
>               rn = "DESAVE";
>               break;
> +        case 2 ... 7:
> +            if (ctx->kscrexist & (1 << sel)) {
> +                tcg_gen_st_tl(arg, cpu_env,
> +                              offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
> +                rn = "KScratch";
> +            }
> +            break;
>           default:
>               goto die;
>           }
> @@ -17490,6 +17533,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, 
> TranslationBlock *tb,
>       ctx.CP0_Config1 = env->CP0_Config1;
>       ctx.tb = tb;
>       ctx.bstate = BS_NONE;
> +    ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
>       /* Restore delay slot state from the tb context.  */
>       ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
>       ctx.ulri = env->CP0_Config3 & (1 << CP0C3_ULRI);