[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 01/28] target-mips: define ISA_MIPS64R6
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 01/28] target-mips: define ISA_MIPS64R6 |
Date: |
Wed, 15 Oct 2014 10:53:53 +0100 |
Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
---
target-mips/mips-defs.h | 28 +++++++++++++++++++---------
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index 9dfa516..6cb62b2 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -30,17 +30,21 @@
#define ISA_MIPS64 0x00000080
#define ISA_MIPS64R2 0x00000100
#define ISA_MIPS32R3 0x00000200
-#define ISA_MIPS32R5 0x00000400
+#define ISA_MIPS64R3 0x00000400
+#define ISA_MIPS32R5 0x00000800
+#define ISA_MIPS64R5 0x00001000
+#define ISA_MIPS32R6 0x00002000
+#define ISA_MIPS64R6 0x00004000
/* MIPS ASEs. */
-#define ASE_MIPS16 0x00001000
-#define ASE_MIPS3D 0x00002000
-#define ASE_MDMX 0x00004000
-#define ASE_DSP 0x00008000
-#define ASE_DSPR2 0x00010000
-#define ASE_MT 0x00020000
-#define ASE_SMARTMIPS 0x00040000
-#define ASE_MICROMIPS 0x00080000
+#define ASE_MIPS16 0x00010000
+#define ASE_MIPS3D 0x00020000
+#define ASE_MDMX 0x00040000
+#define ASE_DSP 0x00080000
+#define ASE_DSPR2 0x00100000
+#define ASE_MT 0x00200000
+#define ASE_SMARTMIPS 0x00400000
+#define ASE_MICROMIPS 0x00800000
/* Chip specific instructions. */
#define INSN_LOONGSON2E 0x20000000
@@ -68,9 +72,15 @@
/* MIPS Technologies "Release 3" */
#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
+#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
/* MIPS Technologies "Release 5" */
#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
+#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5)
+
+/* MIPS Technologies "Release 6" */
+#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
+#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
/* Strictly follow the architecture standard:
- Disallow "special" instruction handling for PMON/SPIM.
--
2.1.0
- [Qemu-devel] [PULL 00/28] target-mips queue, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 01/28] target-mips: define ISA_MIPS64R6,
Leon Alrae <=
- [Qemu-devel] [PULL 02/28] target-mips: signal RI Exception on instructions removed in R6, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 03/28] target-mips: add SELEQZ and SELNEZ instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 04/28] target-mips: move LL and SC instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 05/28] target-mips: extract decode_opc_special* from decode_opc, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 06/28] target-mips: split decode_opc_special* into *_r6 and *_legacy, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 07/28] target-mips: signal RI Exception on DSP and Loongson instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 11/28] target-mips: Status.UX/SX/KX enable 32-bit address wrapping, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 08/28] target-mips: move PREF, CACHE, LLD and SCD instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 09/28] target-mips: redefine Integer Multiply and Divide instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 10/28] target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6, Leon Alrae, 2014/10/15