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[Qemu-devel] [PATCH RFC 6/7] target-arm: use add_i32x4 opcode to handle
From: |
Kirill Batuzov |
Subject: |
[Qemu-devel] [PATCH RFC 6/7] target-arm: use add_i32x4 opcode to handle vadd.i32 instruction |
Date: |
Thu, 16 Oct 2014 12:56:53 +0400 |
Signed-off-by: Kirill Batuzov <address@hidden>
---
target-arm/translate.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 22855d8..00ea5cf 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -5239,6 +5239,18 @@ static int disas_neon_data_insn(CPUARMState * env,
DisasContext *s, uint32_t ins
return 1;
}
+ /* Use vector ops to handle what we can */
+ switch (op) {
+ case NEON_3R_VADD_VSUB:
+ if (!u && size == 2) {
+ tcg_gen_add_i32x4(cpu_Q[rd >> 1], cpu_Q[rn >> 1], cpu_Q[rm
>> 1]);
+ return 0;
+ }
+ break;
+ default:
+ break;
+ }
+
for (pass = 0; pass < (q ? 4 : 2); pass++) {
if (pairwise) {
--
1.7.10.4
- [Qemu-devel] [PATCH RFC 0/7] Translate guest vector operations to host vector operations, Kirill Batuzov, 2014/10/16
- [Qemu-devel] [PATCH RFC 2/7] tcg: store ENV global in TCGContext, Kirill Batuzov, 2014/10/16
- [Qemu-devel] [PATCH RFC 3/7] tcg: add sync_temp opcode, Kirill Batuzov, 2014/10/16
- [Qemu-devel] [PATCH RFC 5/7] target-arm: support access to 128-bit guest registers as globals, Kirill Batuzov, 2014/10/16
- [Qemu-devel] [PATCH RFC 1/7] tcg: add support for 128bit vector type, Kirill Batuzov, 2014/10/16
- [Qemu-devel] [PATCH RFC 7/7] tcg/i386: add support for vector opcodes, Kirill Batuzov, 2014/10/16
- [Qemu-devel] [PATCH RFC 6/7] target-arm: use add_i32x4 opcode to handle vadd.i32 instruction,
Kirill Batuzov <=
- [Qemu-devel] [PATCH RFC 4/7] tcg: add add_i32x4 opcode, Kirill Batuzov, 2014/10/16
- Re: [Qemu-devel] [PATCH RFC 0/7] Translate guest vector operations to host vector operations, Alex Bennée, 2014/10/16