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Re: [Qemu-devel] [PATCH 4/6] target-mips: add restrictions for possible
From: |
Leon Alrae |
Subject: |
Re: [Qemu-devel] [PATCH 4/6] target-mips: add restrictions for possible values in registers |
Date: |
Tue, 21 Oct 2014 14:54:31 +0100 |
User-agent: |
Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 |
On 20/10/2014 11:19, Yongbok Kim wrote:
>> void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
>> {
>> - env->CP0_Wired = arg1 % env->tlb->nb_tlb;
>> + if (env->insn_flags & ISA_MIPS32R6) {
>> + if (arg1 < env->tlb->nb_tlb) {
>> + env->CP0_Wired = arg1;
>
> Wired field should be compared with Limit field (and as a result, number
> of entries in the TLB).
>From spec's point of view the implementation is correct. It supports
"Limit = 0" - maximum number of wired entries is equal to the number of
TLB entries minus one. Obviously we will have to add Limit field once we
decide to support Limit > 0.
>
>> + }
>> + } else {
>> + env->CP0_Wired = arg1 % env->tlb->nb_tlb;
>> + }
>> }
>>
>> void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
>> @@ -1368,11 +1379,14 @@ void helper_mtc0_entryhi(CPUMIPSState *env,
>> target_ulong arg1)
>> }
>>
>> /* 1k pages not implemented */
>> - val = arg1 & mask;
>> #if defined(TARGET_MIPS64)
>> - val &= env->SEGMask;
>> + if ((env->insn_flags & ISA_MIPS32R6) && extract64(arg1, 62, 2) == 0x2) {
>> + mask &= ~(0x3ull << 62);
>
> If Config0_AT = 1, R field is restricted for 1 as well.
Good spot, thanks.
Regards,
Leon