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[Qemu-devel] [PATCH v7 26/32] target-arm: make IFSR banked
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v7 26/32] target-arm: make IFSR banked |
Date: |
Tue, 21 Oct 2014 11:55:38 -0500 |
From: Fabian Aggeler <address@hidden>
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
IFSR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
---
target-arm/cpu.h | 10 +++++++++-
target-arm/helper.c | 9 +++++----
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 9392769..261b881 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -251,7 +251,15 @@ typedef struct CPUARMState {
uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
uint64_t hcr_el2; /* Hypervisor configuration register */
uint64_t scr_el3; /* Secure configuration register. */
- uint32_t ifsr_el2; /* Fault status registers. */
+ union { /* Fault status registers. */
+ struct {
+ uint32_t ifsr_ns;
+ uint32_t ifsr_s;
+ };
+ struct {
+ uint32_t ifsr32_el2;
+ };
+ };
uint64_t esr_el[4];
uint32_t c6_region[8]; /* MPU base/size registers. */
uint64_t far_el[4]; /* Fault address registers. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 903207a..7498f71 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1666,8 +1666,9 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
.fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
.resetfn = arm_cp_reset_ignore, },
{ .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.ifsr_el2), .resetvalue = 0, },
+ .access = PL1_RW, .resetvalue = 0,
+ .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifsr_s),
+ offsetof(CPUARMState, cp15.ifsr_ns) } },
{ .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
.access = PL1_RW,
@@ -4355,11 +4356,11 @@ void arm_cpu_do_interrupt(CPUState *cs)
env->exception.fsr = 2;
/* Fall through to prefetch abort. */
case EXCP_PREFETCH_ABORT:
- env->cp15.ifsr_el2 = env->exception.fsr;
+ A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 32, 32,
env->exception.vaddress);
qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
- env->cp15.ifsr_el2, (uint32_t)env->exception.vaddress);
+ env->exception.fsr, (uint32_t)env->exception.vaddress);
new_mode = ARM_CPU_MODE_ABT;
addr = 0x0c;
mask = CPSR_A | CPSR_I;
--
1.8.3.2
- [Qemu-devel] [PATCH v7 15/32] target-arm: implement IRQ/FIQ routing to Monitor mode, (continued)
- [Qemu-devel] [PATCH v7 15/32] target-arm: implement IRQ/FIQ routing to Monitor mode, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 16/32] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 17/32] target-arm: add NSACR register, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 19/32] target-arm: add MVBAR support, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 12/32] target-arm: add secure state bit to CPREG hash, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 20/32] target-arm: add SCTLR_EL3 and make SCTLR banked, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 18/32] target-arm: add SDER definition, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 21/32] target-arm: make CSSELR banked, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 24/32] target-arm: make c2_mask and c2_base_mask banked, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 22/32] target-arm: add TTBR0_EL3 and make TTBR0/1 banked, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 26/32] target-arm: make IFSR banked,
Greg Bellows <=
- [Qemu-devel] [PATCH v7 27/32] target-arm: make DFSR banked, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 23/32] target-arm: add TCR_EL3 and make TTBCR banked, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 28/32] target-arm: make IFAR/DFAR banked, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 29/32] target-arm: make PAR banked, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 30/32] target-arm: make c13 cp regs banked (FCSEIDR, ...), Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 31/32] target-arm: make MAIR0/1 banked, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 32/32] target-arm: add cpu feature EL3 to CPUs with Security Extensions, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 25/32] target-arm: make DACR banked, Greg Bellows, 2014/10/21
- Re: [Qemu-devel] [PATCH v7 00/32] target-arm: add Security Extensions for CPUs, Peter Maydell, 2014/10/23