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Re: [Qemu-devel] [PATCH v7 04/32] target-arm: rename arm_current_pl to a
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v7 04/32] target-arm: rename arm_current_pl to arm_current_el |
Date: |
Thu, 23 Oct 2014 15:53:16 +0100 |
On 21 October 2014 17:55, Greg Bellows <address@hidden> wrote:
> Renamed the arm_current_pl CPU function to more accurately represent that it
> returns the ARMv8 EL rather than ARMv7 PL.
>
> Signed-off-by: Greg Bellows <address@hidden>
> Reviewed-by: Peter Maydell <address@hidden>
> @@ -1485,7 +1485,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
> gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16));
> break;
> case 2:
> - if (s->current_pl == 0) {
> + if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el == 0) {
> unallocated_encoding(s);
> break;
> }
> @@ -1498,7 +1498,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
> gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16));
> break;
> case 3:
> - if (s->current_pl == 0) {
> + if (!arm_dc_feature(s, ARM_FEATURE_EL3) || s->current_el == 0) {
> unallocated_encoding(s);
> break;
> }
These hunks introduce spurious changes which break PSCI booting
of AArch64. I will fix up in target-arm.next.
thanks
-- PMM
- [Qemu-devel] [PATCH v7 01/32] target-arm: increase arrays of registers R13 & R14, (continued)
- [Qemu-devel] [PATCH v7 01/32] target-arm: increase arrays of registers R13 & R14, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 02/32] target-arm: add arm_is_secure() function, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 05/32] target-arm: make arm_current_el() return EL3, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 10/32] target-arm: add non-secure Translation Block flag, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 08/32] target-arm: add async excp target_el function, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 07/32] target-arm: extend async excp masking, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 09/32] target-arm: add banked register accessors, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 06/32] target-arm: A32: Emulate the SMC instruction, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 04/32] target-arm: rename arm_current_pl to arm_current_el, Greg Bellows, 2014/10/21
- Re: [Qemu-devel] [PATCH v7 04/32] target-arm: rename arm_current_pl to arm_current_el,
Peter Maydell <=
- [Qemu-devel] [PATCH v7 11/32] target-arm: add CPREG secure state support, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 13/32] target-arm: insert AArch32 cpregs twice into hashtable, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 14/32] target-arm: move AArch32 SCR into security reglist, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 15/32] target-arm: implement IRQ/FIQ routing to Monitor mode, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 16/32] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 17/32] target-arm: add NSACR register, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 19/32] target-arm: add MVBAR support, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 12/32] target-arm: add secure state bit to CPREG hash, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 20/32] target-arm: add SCTLR_EL3 and make SCTLR banked, Greg Bellows, 2014/10/21
- [Qemu-devel] [PATCH v7 18/32] target-arm: add SDER definition, Greg Bellows, 2014/10/21