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[Qemu-devel] [PATCH v3 00/15] target-mips: add features required in MIPS
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PATCH v3 00/15] target-mips: add features required in MIPS64R6 |
Date: |
Fri, 24 Oct 2014 13:42:14 +0100 |
This is the next version of patchset containing mainly MIPS64R6 Privileged
Resource Architecture changes and it complements the existing MIPS64R6
support in QEMU.
This patchset is concatenated from the following series which have been on
the mailing list for a while:
http://lists.gnu.org/archive/html/qemu-devel/2014-06/msg04696.html
http://lists.gnu.org/archive/html/qemu-devel/2014-07/msg02292.html
It provides the following set of features:
- KScratch registers
- Read-Inhibit and Execute-Inhibit page protection bits
- TLB Invalidate (TLBINV and TLBINVF instructions)
- BadInstr and BadInstrP
- forbidden slot
- Config5.SBRI bit
- reserved fields and reserved registers (ignore write, read 0)
- updated MIPS64R6-generic CPU
This patchset can be also found on github:
git://github.com/lalrae/qemu.git tags/mips64r6-privileged-v3
Many thanks to everyone who helped with reviewing this so far.
Leon
v3:
* fix the style issue for softmmu access type enum (Peter Maydell)
* BadInstr(P) should be instantiated per VPE rather than TC (James Hogan)
* store/load tlb fields in cpu_save and cpu_load (Yongbok Kim)
* update log messages to mention forbidden slot (Yongbok Kim)
* check also Config.AT when determining legal EntryHi.R values in mtc0 helper
(Yongbok Kim)
* fix Config4.IE check, read 2 bits instead of just 1
* rebase
v2:
* changed BadInstr implementation - fetching instruction word instead of
generating code to save the last instruction (Aurelien Jarno)
* dropped patch updating cpu configuration - this will be done later, when all
the required features are implemented (Aurelien Jarno)
* modified mtc0 and mfc0 to behave like on the real HW when referring to
an unimplemented cp0 register (Aurelien Jarno)
* updated CPU_SAVE_VERSION (Richard Henderson)
* added a patch to the series providing mmu_access_type enum
Leon Alrae (15):
target-mips: add KScratch registers
softmmu: provide softmmu access type enum
target-mips: distinguish between data load and instruction fetch
target-mips: add RI and XI fields to TLB entry
target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}
target-mips: add new Read-Inhibit and Execute-Inhibit exceptions
target-mips: add TLBINV support
target-mips: add BadInstr and BadInstrP support
target-mips: update cpu_save/cpu_load to support new registers
target-mips: add Config5.SBRI
target-mips: implement forbidden slot
target-mips: CP0_Status.CU0 no longer allows the user to access CP0
target-mips: add restrictions for possible values in registers
target-mips: correctly handle access to unimplemented CP0 register
target-mips: enable features in MIPS64R6-generic CPU
disas/mips.c | 2 +
include/exec/cpu-common.h | 6 +
softmmu_template.h | 26 +-
target-mips/cpu.h | 55 +++-
target-mips/helper.c | 104 +++++-
target-mips/helper.h | 7 +
target-mips/machine.c | 26 +-
target-mips/op_helper.c | 183 +++++++++--
target-mips/translate.c | 737 +++++++++++++++++++++++++++----------------
target-mips/translate_init.c | 15 +-
10 files changed, 826 insertions(+), 335 deletions(-)
--
2.1.0
- [Qemu-devel] [PATCH v3 00/15] target-mips: add features required in MIPS64R6,
Leon Alrae <=
- [Qemu-devel] [PATCH v3 01/15] target-mips: add KScratch registers, Leon Alrae, 2014/10/24
- [Qemu-devel] [PATCH v3 02/15] softmmu: provide softmmu access type enum, Leon Alrae, 2014/10/24
- [Qemu-devel] [PATCH v3 03/15] target-mips: distinguish between data load and instruction fetch, Leon Alrae, 2014/10/24
- [Qemu-devel] [PATCH v3 04/15] target-mips: add RI and XI fields to TLB entry, Leon Alrae, 2014/10/24
- [Qemu-devel] [PATCH v3 05/15] target-mips: update PageGrain and m{t, f}c0 EntryLo{0, 1}, Leon Alrae, 2014/10/24
- [Qemu-devel] [PATCH v3 07/15] target-mips: add TLBINV support, Leon Alrae, 2014/10/24
- [Qemu-devel] [PATCH v3 06/15] target-mips: add new Read-Inhibit and Execute-Inhibit exceptions, Leon Alrae, 2014/10/24
- [Qemu-devel] [PATCH v3 08/15] target-mips: add BadInstr and BadInstrP support, Leon Alrae, 2014/10/24