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Re: [Qemu-devel] [PATCH v8 06/27] target-arm: add secure state bit to CP
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v8 06/27] target-arm: add secure state bit to CPREG hash |
Date: |
Fri, 31 Oct 2014 12:31:45 +0000 |
On 31 October 2014 12:28, Peter Maydell <address@hidden> wrote:
> On 30 October 2014 21:28, Greg Bellows <address@hidden> wrote:
>> static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
>> void *opaque, int state,
>> - int crm, int opc1, int opc2)
>> + int crm, int opc1, int opc2, int nsbit)
>
> Again, I think I'd rather we put 'nsbit' after 'state' rather than at the end.
> Also you probably want 'bool ns' rather than 'int nsbit'.
...actually, what you want here is "int secstate" and pass in either
ARM_CP_SECSTATE_S or ARM_CP_SECSTATE_NS. (This matches the way the
'state' parameter takes one of the ARM_CP_STATE_* values.)
-- PMM
- [Qemu-devel] [PATCH v8 03/27] target-arm: add banked register accessors, (continued)
- [Qemu-devel] [PATCH v8 03/27] target-arm: add banked register accessors, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 14/27] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 15/27] target-arm: make CSSELR banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 07/27] target-arm: insert AArch32 cpregs twice into hashtable, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 06/27] target-arm: add secure state bit to CPREG hash, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 02/27] target-arm: add async excp target_el function, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 26/27] target-arm: make MAIR0/1 banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 09/27] target-arm: implement IRQ/FIQ routing to Monitor mode, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 13/27] target-arm: add SCTLR_EL3 and make SCTLR banked, Greg Bellows, 2014/10/31