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[Qemu-devel] [PATCH v2 01/16] hw/intc/arm_gic: Request FIQ sources
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v2 01/16] hw/intc/arm_gic: Request FIQ sources |
Date: |
Thu, 30 Oct 2014 17:11:57 -0500 |
From: Fabian Aggeler <address@hidden>
Preparing for FIQ lines from GIC to CPUs, which is needed for GIC
Security Extensions.
Signed-off-by: Fabian Aggeler <address@hidden>
---
hw/intc/arm_gic.c | 3 +++
include/hw/intc/arm_gic_common.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 270ce05..ea05f8f 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -789,6 +789,9 @@ void gic_init_irqs_and_distributor(GICState *s)
for (i = 0; i < NUM_CPU(s); i++) {
sysbus_init_irq(sbd, &s->parent_irq[i]);
}
+ for (i = 0; i < NUM_CPU(s); i++) {
+ sysbus_init_irq(sbd, &s->parent_fiq[i]);
+ }
memory_region_init_io(&s->iomem, OBJECT(s), &gic_dist_ops, s,
"gic_dist", 0x1000);
}
diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h
index f6887ed..01c6f24 100644
--- a/include/hw/intc/arm_gic_common.h
+++ b/include/hw/intc/arm_gic_common.h
@@ -50,6 +50,7 @@ typedef struct GICState {
/*< public >*/
qemu_irq parent_irq[GIC_NCPU];
+ qemu_irq parent_fiq[GIC_NCPU];
bool enabled;
bool cpu_enabled[GIC_NCPU];
--
1.8.3.2
- [Qemu-devel] [PATCH v2 00/16] target-arm: Add GICv1/SecExt and GICv2/Grouping, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 15/16] hw/intc/arm_gic: Break out gic_update() function, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 14/16] hw/intc/arm_gic: Restrict priority view, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 11/16] hw/intc/arm_gic: Handle grouping for GICC_HPPIR, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 05/16] hw/intc/arm_gic: Add ns_access() function, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 01/16] hw/intc/arm_gic: Request FIQ sources,
Greg Bellows <=
- [Qemu-devel] [PATCH v2 10/16] hw/intc/arm_gic: Implement Non-secure view of RPR, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 03/16] hw/arm/virt.c: Wire FIQ between CPU <> GIC, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 16/16] hw/intc/arm_gic: add gic_update() for grouping, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 08/16] hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 09/16] hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 07/16] hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 13/16] hw/intc/arm_gic: Change behavior of IAR writes, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 02/16] hw/arm/vexpress.c: Wire FIQ between CPU <> GIC, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 04/16] hw/intc/arm_gic: Add Security Extensions property, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 12/16] hw/intc/arm_gic: Change behavior of EOIR writes, Greg Bellows, 2014/10/31