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[Qemu-devel] [PATCH v2 12/16] hw/intc/arm_gic: Change behavior of EOIR w
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v2 12/16] hw/intc/arm_gic: Change behavior of EOIR writes |
Date: |
Thu, 30 Oct 2014 17:12:08 -0500 |
From: Fabian Aggeler <address@hidden>
Grouping (GICv2) and Security Extensions change the behavior of EOIR
writes. Completing Group0 interrupts is only allowed from Secure state
and completing Group1 interrupts from Secure state is only allowed if
AckCtl bit is set.
Signed-off-by: Fabian Aggeler <address@hidden>
---
v1 -> v2
- Fix issue with EOIR writes involving AckCtl. AckCtl is ignored on EOIR
group 1 interrupts when non-secure. Group 1 interrupts are only ignored when
secure and AckCTl is clear.
---
hw/intc/arm_gic.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 15fd660..2d83225 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -384,6 +384,21 @@ void gic_complete_irq(GICState *s, int cpu, int irq)
GIC_SET_PENDING(irq, cm);
update = 1;
}
+ } else if ((s->revision >= 2 && !s->security_extn)
+ || (s->security_extn && !ns_access())) {
+ /* Handle GICv2 without Security Extensions or GIC with Security
+ * Extensions and a secure write.
+ */
+ if (!GIC_TEST_GROUP0(irq, cm) && !ns_access()
+ && !(s->cpu_control[cpu][0] & GICC_CTLR_S_ACK_CTL)) {
+ /* Unpredictable. We choose to ignore. */
+ DPRINTF("EOI for Group1 interrupt %d ignored "
+ "(AckCtl disabled)\n", irq);
+ return;
+ }
+ } else if (s->security_extn && ns_access() && GIC_TEST_GROUP0(irq, cm)) {
+ DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq);
+ return;
}
if (irq != s->running_irq[cpu]) {
--
1.8.3.2
- [Qemu-devel] [PATCH v2 01/16] hw/intc/arm_gic: Request FIQ sources, (continued)
- [Qemu-devel] [PATCH v2 01/16] hw/intc/arm_gic: Request FIQ sources, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 10/16] hw/intc/arm_gic: Implement Non-secure view of RPR, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 03/16] hw/arm/virt.c: Wire FIQ between CPU <> GIC, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 16/16] hw/intc/arm_gic: add gic_update() for grouping, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 08/16] hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 09/16] hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 07/16] hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 13/16] hw/intc/arm_gic: Change behavior of IAR writes, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 02/16] hw/arm/vexpress.c: Wire FIQ between CPU <> GIC, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 04/16] hw/intc/arm_gic: Add Security Extensions property, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 12/16] hw/intc/arm_gic: Change behavior of EOIR writes,
Greg Bellows <=
- [Qemu-devel] [PATCH v2 06/16] hw/intc/arm_gic: Add Interrupt Group Registers, Greg Bellows, 2014/10/31