Re: [Qemu-devel] [PATCH v8 10/27] target-arm: add NSACR register

[Greg Bellows]

On 31 October 2014 08:24, Peter Maydell <address@hidden> wrote:

On 30 October 2014 21:28, Greg Bellows <address@hidden> wrote:
> From: Fabian Aggeler <address@hidden>
>
> Implements NSACR register with corresponding read/write functions
> for ARMv7 and ARMv8.
>
> Signed-off-by: Sergey Fedorov <address@hidden>
> Signed-off-by: Fabian Aggeler <address@hidden>
> Signed-off-by: Greg Bellows <address@hidden>
>
> ---
>
> v7 -> v8
> - Update naming from c1_nsacr to nsacr to match other registers being changed.
> - Remove NSACR read/write functions
>
> v4 -> v5
> - Changed to use renamed arm_current_el()
> ---
>  target-arm/cpu.h    | 6 ++++++
>  target-arm/helper.c | 3 +++
>  2 files changed, 9 insertions(+)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 6bb7d39..88e22fb 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -181,6 +181,7 @@ typedef struct CPUARMState {
>          uint64_t c1_sys; /* System control register.  */
>          uint64_t c1_coproc; /* Coprocessor access register.  */
>          uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
> +        uint32_t nsacr; /* Non-secure access control register. */
>          uint64_t ttbr0_el1; /* MMU translation table base 0. */
>          uint64_t ttbr1_el1; /* MMU translation table base 1. */
>          uint64_t c2_control; /* MMU translation table base control.  */
> @@ -634,6 +635,11 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
>  #define SCR_AARCH32_MASK      (0x3fff & ~(SCR_RW | SCR_ST))
>  #define SCR_AARCH64_MASK      (0x3fff & ~SCR_NET)
>
> +#define NSACR_NSTRCDIS (1U << 20)
> +#define NSACR_RFR      (1U << 19)
> +#define NSACR_NSASEDIS (1U << 15)
> +#define NSACR_NSD32DIS (1U << 14)

Not sure there's much point defining bit constants we don't use
(these don't match the v8 bits anyway).

Agree (was using them before).  Removed in v9.

 

> +
>  /* Return the current FPSCR value.  */
>  uint32_t vfp_get_fpscr(CPUARMState *env);
>  void vfp_set_fpscr(CPUARMState *env, uint32_t val);
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index e73756d..3c12eb3 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2344,6 +2344,9 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
>        .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
>        .access = PL3_RW, .resetvalue = 0, .writefn = scr_write,
>        .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3) },
> +    { .name = "NSACR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 2,
> +      .access = PL3_RW | PL1_R, .resetvalue = 0,
> +      .fieldoffset = offsetof(CPUARMState, cp15.nsacr) },

PL1_R implies PL3_R, so you can write the access value as
PL3_W | PL1_R.

Updated in v9.

 

It would be good to have a comment
   /* TODO: implement trapping of secure EL1 reads and writes to EL3. */

Added in v9.

 

>      REGINFO_SENTINEL
>  };
>
> --
> 1.8.3.2

Otherwise
Reviewed-by: Peter Maydell <address@hidden>

thanks
-- PMM