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Re: [Qemu-devel] [PATCH v9 01/26] target-arm: extend async excp masking
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v9 01/26] target-arm: extend async excp masking |
Date: |
Wed, 5 Nov 2014 23:37:01 +0000 |
On 5 November 2014 23:22, Greg Bellows <address@hidden> wrote:
> This patch extends arm_excp_unmasked() to use lookup tables for determining
> whether IRQ and FIQ exceptions are masked. The lookup tables are based on the
> ARMv8 and ARMv7 specification physical interrupt masking tables.
>
> If EL3 is using AArch64 IRQ/FIQ masking is ignored in all exception levels
> other than EL3 if SCR.{FIQ|IRQ} is set to 1 (routed to EL3).
>
> Signed-off-by: Greg Bellows <address@hidden>
>
> ---
>
> v8 -> v9
> - Undo the use of tables for exception masking and instead go with simplified
> logic based on the target EL lookup.
> - Remove the masking tables
>
> v7 -> v8
> - Add IRQ and FIQ exeception masking lookup tables.
> - Rewrite patch to use lookup tables for determining whether an excpetion is
> masked or not.
>
> v5 -> v6
> - Globally change Aarch# to AArch#
> - Fixed comment termination
>
> v4 -> v5
> - Merge with v4 patch 10
> ---
> target-arm/cpu.h | 79
> +++++++++++++++++++++++++++++++++++++-------------------
> 1 file changed, 53 insertions(+), 26 deletions(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index cb6ec5c..0ea8602 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -1247,39 +1247,51 @@ static inline bool arm_excp_unmasked(CPUState *cs,
> unsigned int excp_idx)
> CPUARMState *env = cs->env_ptr;
> unsigned int cur_el = arm_current_el(env);
> unsigned int target_el = arm_excp_target_el(cs, excp_idx);
> - /* FIXME: Use actual secure state. */
> - bool secure = false;
> - /* If in EL1/0, Physical IRQ routing to EL2 only happens from NS state.
> */
> - bool irq_can_hyp = !secure && cur_el < 2 && target_el == 2;
> - /* ARMv7-M interrupt return works by loading a magic value
> - * into the PC. On real hardware the load causes the
> - * return to occur. The qemu implementation performs the
> - * jump normally, then does the exception return when the
> - * CPU tries to execute code at the magic address.
> - * This will cause the magic PC value to be pushed to
> - * the stack if an interrupt occurred at the wrong time.
> - * We avoid this by disabling interrupts when
> - * pc contains a magic address.
I did suggest you based this on the M profile patches;
you'll find this doesn't apply to current master I think.
thanks
-- PMM
- [Qemu-devel] [PATCH v9 00/26] target-arm: add Security Extensions for CPUs, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 01/26] target-arm: extend async excp masking, Greg Bellows, 2014/11/05
- Re: [Qemu-devel] [PATCH v9 01/26] target-arm: extend async excp masking,
Peter Maydell <=
- [Qemu-devel] [PATCH v9 03/26] target-arm: add banked register accessors, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 04/26] target-arm: add non-secure Translation Block flag, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 02/26] target-arm: add async excp target_el function, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 05/26] target-arm: add CPREG secure state support, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 06/26] target-arm: add secure state bit to CPREG hash, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 08/26] target-arm: move AArch32 SCR into security reglist, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 07/26] target-arm: insert AArch32 cpregs twice into hashtable, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 09/26] target-arm: implement IRQ/FIQ routing to Monitor mode, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 10/26] target-arm: add NSACR register, Greg Bellows, 2014/11/05