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[Qemu-devel] [PATCH] target-mips: fix multiple TCG registers covering sa
From: |
Yongbok Kim |
Subject: |
[Qemu-devel] [PATCH] target-mips: fix multiple TCG registers covering same data |
Date: |
Fri, 7 Nov 2014 10:43:21 +0000 |
Avoid to allocate different TCG registers for the FPU registers
that are mapped on the MSA vectore registers.
Signed-off-by: Yongbok Kim <address@hidden>
---
target-mips/translate.c | 8 +++-----
1 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index b43b286..95d8071 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -20200,14 +20200,12 @@ void mips_tcg_init(void)
regnames[i]);
for (i = 0; i < 32; i++) {
- int off = offsetof(CPUMIPSState, active_fpu.fpr[i]);
- fpu_f64[i] = tcg_global_mem_new_i64(TCG_AREG0, off, fregnames[i]);
- }
-
- for (i = 0; i < 32; i++) {
int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
msa_wr_d[i * 2] =
tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2]);
+ /* The scalar floating-point unit (FPU) registers are mapped on
+ * the MSA vector registers. */
+ fpu_f64[i] = msa_wr_d[i * 2];
off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
msa_wr_d[i * 2 + 1] =
tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2 + 1]);
--
1.7.4
- [Qemu-devel] [PATCH] target-mips: fix multiple TCG registers covering same data,
Yongbok Kim <=