Re: [Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits

[Leon Alrae]

On 05/11/2014 15:26, Leon Alrae wrote:
> On 04/11/2014 15:41, Maciej W. Rozycki wrote:
>> Set the CP0.Config3.DSP2P bit for the 74kf processor and both that bit 
>> and the CP0.Config3.DSP bit for the artificial mips32r5-generic and 
>> mips64dspr2 processors.  They have the DSPr2 ASE enabled in `insn_flags' 
>> and CPUs that implement that ASE need to have both CP0.Config3.DSP and 
>> CP0.Config3.DSP2P set or software won't detect its presence.
>>
>> Signed-off-by: Maciej W. Rozycki <address@hidden>
>> ---
>> qemu-mips-config-dsp.diff
>> Index: qemu-git-trunk/target-mips/translate_init.c
>> ===================================================================
>> --- qemu-git-trunk.orig/target-mips/translate_init.c 2014-11-04 
>> 03:32:21.408100354 +0000
>> +++ qemu-git-trunk/target-mips/translate_init.c      2014-11-04 
>> 03:39:48.458972962 +0000
>> @@ -330,7 +330,8 @@ static const mips_def_t mips_defs[] =
>>                         (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
>>                         (1 << CP0C1_CA),
>>          .CP0_Config2 = MIPS_CONFIG2,
>> -        .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_DSPP),
>> +        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << 
>> CP0C3_DSPP) |
>> +                       (0 << CP0C3_VInt),
>>          .CP0_LLAddr_rw_bitmask = 0,
>>          .CP0_LLAddr_shift = 4,
>>          .SYNCI_Step = 32,
>> @@ -396,7 +397,8 @@ static const mips_def_t mips_defs[] =
>>                         (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
>>                         (1 << CP0C1_CA),
>>          .CP0_Config2 = MIPS_CONFIG2,
>> -        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M),
>> +        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
>> +                       (1 << CP0C3_DSPP),
>>          .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M),
>>          .CP0_Config4_rw_bitmask = 0,
>>          .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR),
>> @@ -677,7 +679,8 @@ static const mips_def_t mips_defs[] =
>>                         (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
>>                         (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
>>          .CP0_Config2 = MIPS_CONFIG2,
>> -        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
>> +        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
>> +                       (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
>>          .CP0_LLAddr_rw_bitmask = 0,
>>          .CP0_LLAddr_shift = 0,
>>          .SYNCI_Step = 32,
>>

When I've been applying this patch to my mips-next candidate branch for
2.2 I realized that you haven't rebased it onto the recent version where
MSA has been added to mips32r5-generic. Now I don't think that having
DSP and MSA on one CPU makes sense, therefore what I'm going to do is to
change mips32r5-generic part in your patch slightly: instead of setting
CP0.Config3.DSP/DSP2P the patch will remove ASE_DSP/DSPR2 insn_flags.

Regards,
Leon