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[Qemu-devel] [PULL 7/7] target-mips: fix multiple TCG registers covering
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 7/7] target-mips: fix multiple TCG registers covering same data |
Date: |
Fri, 7 Nov 2014 16:56:09 +0000 |
From: Yongbok Kim <address@hidden>
Avoid to allocate different TCG registers for the FPU registers
that are mapped on the MSA vectore registers.
Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/translate.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 0bea3c4..f0b8e6f 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -19285,14 +19285,12 @@ void mips_tcg_init(void)
regnames[i]);
for (i = 0; i < 32; i++) {
- int off = offsetof(CPUMIPSState, active_fpu.fpr[i]);
- fpu_f64[i] = tcg_global_mem_new_i64(TCG_AREG0, off, fregnames[i]);
- }
-
- for (i = 0; i < 32; i++) {
int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
msa_wr_d[i * 2] =
tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2]);
+ /* The scalar floating-point unit (FPU) registers are mapped on
+ * the MSA vector registers. */
+ fpu_f64[i] = msa_wr_d[i * 2];
off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
msa_wr_d[i * 2 + 1] =
tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2 + 1]);
--
2.1.0
- [Qemu-devel] [PULL 0/7] target-mips queue, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 1/7] mips: Remove CONFIG_VT82C686 from non-Fulong configs, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 2/7] mips: Respect CP0.Status.CU1 for microMIPS FP branches, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 3/7] mips: Add macros for CP0.Config3 and CP0.Config4 bits, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 4/7] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 7/7] target-mips: fix multiple TCG registers covering same data,
Leon Alrae <=
- [Qemu-devel] [PULL 6/7] mips: Ensure PC update with MTC0 single-stepping, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 5/7] target-mips: fix for missing delay slot in BC1EQZ and BC1NEZ, Leon Alrae, 2014/11/07
- Re: [Qemu-devel] [PULL 0/7] target-mips queue, Peter Maydell, 2014/11/10