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Re: [Qemu-devel] [PATCH v2 4/4] target-tricore: Add instructions of RCR
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v2 4/4] target-tricore: Add instructions of RCR opcode format |
Date: |
Fri, 14 Nov 2014 14:39:46 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 |
On 11/13/2014 06:12 PM, Bastian Koppelmann wrote:
> + tcg_gen_ext_i32_i64(t3, r3);
> + tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
> + /* extend the sign for r2 to high 64 bits */
> + tcg_gen_sari_i64(t4, t2, 63);
> + tcg_gen_ext_i32_i64(t1, r1);
> +
> + tcg_gen_muls2_i64(t1, t3, t1, t3);
> + tcg_gen_add2_i64(t1, t3, t2, t4, t1, t3);
> +
I don't believe that you need 128 bit arithemetic for multiply-accumulate,
either here or elsewhere (e.g. msub).
Looking at unsigned, the maximum result of the multiply is 2*(2^n-1), or 2^(2n)
- 2^(n+1). Which means that the accumulate with a 2^n-1 value cannot overflow
a double-word intermediate result.
r~
- [Qemu-devel] [PATCH v2 0/4] Add TriCore RCPW, RCRR, RCRW, RLC and RCR instructions, Bastian Koppelmann, 2014/11/13
- [Qemu-devel] [PATCH v2 2/4] target-tricore: Add instructions of RCPW, RCRR and RCRW opcode format, Bastian Koppelmann, 2014/11/13
- [Qemu-devel] [PATCH v2 1/4] target-tricore: Make TRICORE_FEATURES implying others., Bastian Koppelmann, 2014/11/13
- [Qemu-devel] [PATCH v2 3/4] target-tricore: Add instructions of RLC opcode format, Bastian Koppelmann, 2014/11/13
- [Qemu-devel] [PATCH v2 4/4] target-tricore: Add instructions of RCR opcode format, Bastian Koppelmann, 2014/11/13
- Re: [Qemu-devel] [PATCH v2 4/4] target-tricore: Add instructions of RCR opcode format,
Richard Henderson <=
- Re: [Qemu-devel] [PATCH v2 0/4] Add TriCore RCPW, RCRR, RCRW, RLC and RCR instructions, Richard Henderson, 2014/11/14