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[Qemu-devel] [PATCH v11 15/26] target-arm: make CSSELR banked
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v11 15/26] target-arm: make CSSELR banked |
Date: |
Mon, 17 Nov 2014 10:47:47 -0600 |
From: Fabian Aggeler <address@hidden>
Rename CSSELR (cache size selection register) and add secure
instance (AArch32).
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
---
v8 -> v9
- Replaced call to ARM_CP_SECSTATE_TEST with direct access
v7 -> v8
- Fix CSSELR CP register definition to use .opc0 rather than .cp.
v5 -> v6
- Changed _el field variants to be array based
- Switch to use distinct CPREG secure flags.
- Merged CSSELR and CSSELR_EL1 reginfo entries
v4 -> v5
- Changed to use the CCSIDR cpreg bank flag to select the csselr bank instead
of the A32_BANKED macro. This more accurately uses the secure state bank
matching the CCSIDR.
---
target-arm/cpu.h | 10 +++++++++-
target-arm/helper.c | 14 +++++++++++---
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 6559aa8..f06d209 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -177,7 +177,15 @@ typedef struct CPUARMState {
/* System control coprocessor (cp15) */
struct {
uint32_t c0_cpuid;
- uint64_t c0_cssel; /* Cache size selection. */
+ union { /* Cache size selection */
+ struct {
+ uint64_t _unused_csselr0;
+ uint64_t csselr_ns;
+ uint64_t _unused_csselr1;
+ uint64_t csselr_s;
+ };
+ uint64_t csselr_el[4];
+ };
union { /* System control register. */
struct {
uint64_t _unused_sctlr;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d555fe4..05e66fb 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -776,7 +776,14 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo
*ri, uint64_t value)
static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
ARMCPU *cpu = arm_env_get_cpu(env);
- return cpu->ccsidr[env->cp15.c0_cssel];
+
+ /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
+ * bank
+ */
+ uint32_t index = A32_BANKED_REG_GET(env, csselr,
+ ri->secure & ARM_CP_SECSTATE_S);
+
+ return cpu->ccsidr[index];
}
static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -903,8 +910,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
{ .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
- .writefn = csselr_write, .resetvalue = 0 },
+ .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
+ .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
+ offsetof(CPUARMState, cp15.csselr_ns) } },
/* Auxiliary ID register: this actually has an IMPDEF value but for now
* just RAZ for all cores:
*/
--
1.8.3.2
- [Qemu-devel] [PATCH v11 05/26] target-arm: add CPREG secure state support, (continued)
- [Qemu-devel] [PATCH v11 05/26] target-arm: add CPREG secure state support, Greg Bellows, 2014/11/17
- [Qemu-devel] [PATCH v11 06/26] target-arm: add secure state bit to CPREG hash, Greg Bellows, 2014/11/17
- [Qemu-devel] [PATCH v11 08/26] target-arm: move AArch32 SCR into security reglist, Greg Bellows, 2014/11/17
- [Qemu-devel] [PATCH v11 07/26] target-arm: insert AArch32 cpregs twice into hashtable, Greg Bellows, 2014/11/17
- [Qemu-devel] [PATCH v11 09/26] target-arm: implement IRQ/FIQ routing to Monitor mode, Greg Bellows, 2014/11/17
- [Qemu-devel] [PATCH v11 10/26] target-arm: add NSACR register, Greg Bellows, 2014/11/17
- [Qemu-devel] [PATCH v11 11/26] target-arm: add SDER definition, Greg Bellows, 2014/11/17
- [Qemu-devel] [PATCH v11 12/26] target-arm: add MVBAR support, Greg Bellows, 2014/11/17
- [Qemu-devel] [PATCH v11 14/26] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI, Greg Bellows, 2014/11/17
- [Qemu-devel] [PATCH v11 13/26] target-arm: add SCTLR_EL3 and make SCTLR banked, Greg Bellows, 2014/11/17
- [Qemu-devel] [PATCH v11 15/26] target-arm: make CSSELR banked,
Greg Bellows <=
- [Qemu-devel] [PATCH v11 16/26] target-arm: make TTBR0/1 banked, Greg Bellows, 2014/11/17
- [Qemu-devel] [PATCH v11 17/26] target-arm: make TTBCR banked, Greg Bellows, 2014/11/17
- [Qemu-devel] [PATCH v11 18/26] target-arm: make DACR banked, Greg Bellows, 2014/11/17
- [Qemu-devel] [PATCH v11 19/26] target-arm: make IFSR banked, Greg Bellows, 2014/11/17
- [Qemu-devel] [PATCH v11 20/26] target-arm: make DFSR banked, Greg Bellows, 2014/11/17
- [Qemu-devel] [PATCH v11 21/26] target-arm: make IFAR/DFAR banked, Greg Bellows, 2014/11/17
- [Qemu-devel] [PATCH v11 23/26] target-arm: make VBAR banked, Greg Bellows, 2014/11/17
- [Qemu-devel] [PATCH v11 24/26] target-arm: make c13 cp regs banked (FCSEIDR, ...), Greg Bellows, 2014/11/17
- [Qemu-devel] [PATCH v11 22/26] target-arm: make PAR banked, Greg Bellows, 2014/11/17
- [Qemu-devel] [PATCH v11 26/26] target-arm: add cpu feature EL3 to CPUs with Security Extensions, Greg Bellows, 2014/11/17