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Re: [Qemu-devel] [PATCH v2 4/4] target-tricore: Add instructions of RCR


From: Bastian Koppelmann
Subject: Re: [Qemu-devel] [PATCH v2 4/4] target-tricore: Add instructions of RCR opcode format
Date: Wed, 19 Nov 2014 13:35:47 +0000
User-agent: Mozilla/5.0 (X11; Linux i686; rv:31.0) Gecko/20100101 Thunderbird/31.2.0


On 11/14/2014 01:39 PM, Richard Henderson wrote:
On 11/13/2014 06:12 PM, Bastian Koppelmann wrote:
+    tcg_gen_ext_i32_i64(t3, r3);
+    tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
+    /* extend the sign for r2 to high 64 bits */
+    tcg_gen_sari_i64(t4, t2, 63);
+    tcg_gen_ext_i32_i64(t1, r1);
+
+    tcg_gen_muls2_i64(t1, t3, t1, t3);
+    tcg_gen_add2_i64(t1, t3, t2, t4, t1, t3);
+
I don't believe that you need 128 bit arithemetic for multiply-accumulate,
either here or elsewhere (e.g. msub).

Looking at unsigned, the maximum result of the multiply is 2*(2^n-1), or 2^(2n)
- 2^(n+1).  Which means that the accumulate with a 2^n-1 value cannot overflow
a double-word intermediate result.
Madd.u has the following signature 64 + (32 * 32) --> 64, as far as I read the documentation, and would result as you described in a max result of 2^(2n) - 2^(n+1) for the multiplication, but it would accumulate with 2^(2n) -1, which can definitly overflow, with n = 32.

However for signed multiply accumulate I don't need 128 bit arithmetic, because only the add/sub operation of those two can overflow. Thanks for the tip!

Cheers,
Bastian



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