[Qemu-devel] [PATCH v3 0/4] Add TriCore RCPW, RCRR, RCRW, RLC and RCR instructions

[Bastian Koppelmann]

Hi,

this patch depends on the previous TriCore patches 
(https://patchwork.ozlabs.org/patch/405459/) and will hopefully end up in 2.3 
QEMU.
Other than adding the RCPW, RCRR, RCRW, RLC and RCR instructions, it cleans up 
how ISA versions in the feature bitmask are handled,
to simplify the checks, when instructions are available.

Thanks,
Bastian

v2 -> v3:
    - madd/msub and maddu/msubu now use 64 bit arithmetic instead of 128 bit.
    - helper madd64_ssov/suov and msub64_ssov/suov now use 64 bit arithmetic 
for the mul.
    - cleaned up double setting of PSW_USB_V/SV in helper_msub64_suov.

Bastian Koppelmann (4):
  target-tricore: Make TRICORE_FEATURES implying others.
  target-tricore: Add instructions of RCPW, RCRR and RCRW opcode format
  target-tricore: Add instructions of RLC opcode format
  target-tricore: Add instructions of RCR opcode format

 target-tricore/cpu.c             |   9 +
 target-tricore/csfr.def          | 124 +++++++
 target-tricore/helper.h          |  11 +
 target-tricore/op_helper.c       | 202 +++++++++++
 target-tricore/translate.c       | 730 ++++++++++++++++++++++++++++++++++++++-
 target-tricore/tricore-opcodes.h |   4 +-
 6 files changed, 1073 insertions(+), 7 deletions(-)
 create mode 100644 target-tricore/csfr.def

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2.1.3