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Re: [Qemu-devel] [PATCH] target-mips: Fix CP0.Config3.ISAOnExc write acc
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From: |
Maciej W. Rozycki |
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Subject: |
Re: [Qemu-devel] [PATCH] target-mips: Fix CP0.Config3.ISAOnExc write accesses |
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Date: |
Tue, 2 Dec 2014 11:44:25 +0000 |
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User-agent: |
Alpine 1.10 (DEB 962 2008-03-14) |
On Tue, 2 Dec 2014, Leon Alrae wrote:
> > Please note that for this validation I'm using an artificial microMIPS
> > processor that also has an FPU implemented, so that our microMIPS FP
> > support is correctly validated too (I don't really know if there exists
> > any real microMIPS processor that includes an FPU; if so, then it would
> > be good to add it to the list our supported configurations).
>
> FYI, there are real CPUs which support microMIPS and include FPU, for
> example microAptivUC.
Good to know, thanks, and good to have real hardware as a reference.
Thanks for your review.
Maciej