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Re: [Qemu-devel] [PATCH] target-mips: Correct 32-bit address space wrapp
From: |
Maciej W. Rozycki |
Subject: |
Re: [Qemu-devel] [PATCH] target-mips: Correct 32-bit address space wrapping |
Date: |
Fri, 5 Dec 2014 18:55:07 +0000 |
User-agent: |
Alpine 1.10 (DEB 962 2008-03-14) |
On Thu, 4 Dec 2014, Leon Alrae wrote:
> > Index: qemu-git-trunk/target-mips/translate.c
> > ===================================================================
> > --- qemu-git-trunk.orig/target-mips/translate.c 2014-11-12
> > 07:41:26.597542010 +0000
> > +++ qemu-git-trunk/target-mips/translate.c 2014-11-12 07:41:26.597542010
> > +0000
> > @@ -10724,6 +10724,7 @@ static void gen_mips16_save (DisasContex
> > {
> > TCGv t0 = tcg_temp_new();
> > TCGv t1 = tcg_temp_new();
> > + TCGv t2 = tcg_temp_new();
> > int args, astatic;
> >
> > switch (aregs) {
> > @@ -10782,7 +10783,8 @@ static void gen_mips16_save (DisasContex
> > gen_load_gpr(t0, 29);
> >
> > #define DECR_AND_STORE(reg) do { \
> > - tcg_gen_subi_tl(t0, t0, 4); \
> > + tcg_gen_movi_tl(t2, -4); \
>
> Wouldn't it be better to move this line outside of the macro to avoid
> generating unnecessary tcg ops? DECR_AND_STORE is called multiple times
> and t2 doesn't change in-between.
It would. This code isn't wrong though unlike our current version,
this is merely a pessimisation. An update will require a costly
regression test rerun and therefore I'll give the priority to the
outstanding changes I have before going back to this change. Thanks for
the tip and your review.
Maciej